利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.024 秒)

    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08116156B2

    公开(公告)日：2012-02-14

    申请号：US12320891

    申请日：2009-02-06

    申请人： Yoshiro Riho ,  Atsushi Fujikawa

    发明人： Yoshiro Riho ,  Atsushi Fujikawa

    IPC分类号： G11C29/00

    CPC分类号： G11C8/10 ,  G11C29/84

    摘要： There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.

    摘要翻译： 提供了一种行预解码器，其对地址进行预编码，而不管请求访问的地址是否是缺陷地址，基于由行预解码器生成的预解码信号来控制子字驱动器的行主解码器，以及 修复确定电路，确定地址是否是有缺陷的地址。 行主解码器，行预解码器和修复确定电路都具有列方向被设置为纵向的形状。 行预解码器和修复确定电路在列方向上彼此相邻布置，并且与行主解码器并行布置。

    Semiconductor memory device
    2.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20090201752A1

    公开(公告)日：2009-08-13

    申请号：US12320891

    申请日：2009-02-06

    申请人： Yoshiro Riho ,  Atsushi Fujikawa

    发明人： Yoshiro Riho ,  Atsushi Fujikawa

    IPC分类号： G11C29/04 ,  G11C8/10 ,  G11C17/16

    CPC分类号： G11C8/10 ,  G11C29/84

    摘要： There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.

    摘要翻译： 提供了一种行预解码器，其对地址进行预编码，而不管请求访问的地址是否是缺陷地址，基于由行预解码器生成的预解码信号来控制子字驱动器的行主解码器，以及 修复确定电路，确定地址是否是有缺陷的地址。 行主解码器，行预解码器和修复确定电路都具有列方向被设置为纵向的形状。 行预解码器和修复确定电路在列方向上彼此相邻布置，并且与行主解码器并行布置。

    Semiconductor device having sense amplifier
    3.
    发明授权
    Semiconductor device having sense amplifier 有权
    具有读出放大器的半导体器件

    公开(公告)号：US08659321B2

    公开(公告)日：2014-02-25

    申请号：US13306560

    申请日：2011-11-29

    申请人： Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

    发明人： Yuko Watanabe ,  Yoshiro Riho ,  Hiromasa Noda ,  Yoji Idei ,  Kosuke Goto

    IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076

    摘要： A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

    摘要翻译： 半导体器件包括用于向读出放大器的第一电源节点提供第一电位的第一驱动器电路，用于向读出放大器的第二电源节点提供第二电位和第三电位的第二和第三驱动器电路，以及 用于控制第一至第三驱动器电路的操作的定时控制电路。 定时控制电路包括用于决定第三驱动电路的接通时间的延迟电路。 延迟电路包括具有取决于外部电源电位的延迟量的第一延迟电路和具有不依赖于外部电源电位的延迟量的第二延迟电路，并且第三驱动电路的导通周期为 基于第一和第二延迟电路的延迟量的总和来决定。

    Semiconductor device and testing method for same
    4.
    发明授权
    Semiconductor device and testing method for same 失效
    半导体器件及其测试方法相同

    公开(公告)号：US07529986B2

    公开(公告)日：2009-05-05

    申请号：US11968664

    申请日：2008-01-03

    申请人： Yoshiro Riho ,  Yutaka Ito

    发明人： Yoshiro Riho ,  Yutaka Ito

    IPC分类号： G11C29/00 ,  G11C7/00 ,  H03M13/00

    CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

    摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

    摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20090003107A1

    公开(公告)日：2009-01-01

    申请号：US12145240

    申请日：2008-06-24

    申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

    发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

    IPC分类号： G11C7/12

    CPC分类号： G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

    摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

    摘要翻译： 半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

    Semiconductor storage device and refresh control method therefor
    6.
    发明授权
    Semiconductor storage device and refresh control method therefor 失效
    半导体存储装置及其刷新控制方法

    公开(公告)号：US07355919B2

    公开(公告)日：2008-04-08

    申请号：US11806438

    申请日：2007-05-31

    申请人： Yoshiro Riho ,  Yutaka Ito

    发明人： Yoshiro Riho ,  Yutaka Ito

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

    摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

    摘要翻译： 动态半导体存储装置，其中待机时间期间的电源电流减小以降低功耗并且抑制芯片面积增加。 在正常操作期间，关于与正常操作期间访问的行地址相关联的字线的信息被存储在RAM中。 在进入自刷新时，读出连接到与正常操作时间期间访问的行地址相关联的字线的存储器单元的数据，并将数据的校验位附加到编码器中并写入校验位区域。 作为上电顺序后的第一自刷新输入的初始化动作，对每个字线检查存储单元的数据保持时间。 基于检查结果，确定字线的刷新周期的设定值并写入RAM中，以设定基于字线的刷新周期。 在错误检查刷新操作期间，错误校正电路校正任何错误。

    Semiconductor storage device and refresh control method therefor
    7.
    发明申请
    Semiconductor storage device and refresh control method therefor 失效

    公开(公告)号：US20070230265A1

    公开(公告)日：2007-10-04

    申请号：US11806438

    申请日：2007-05-31

    申请人： Yoshiro Riho ,  Yutaka Ito

    发明人： Yoshiro Riho ,  Yutaka Ito

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40626 ,  G06F11/1004 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

    摘要： A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

    Refresh control method of a semiconductor memory device and semiconductor memory device
    8.
    发明申请
    Refresh control method of a semiconductor memory device and semiconductor memory device 失效
    半导体存储器件和半导体存储器件的刷新控制方法

    公开(公告)号：US20060087903A1

    公开(公告)日：2006-04-27

    申请号：US11254722

    申请日：2005-10-21

    申请人： Yoshiro Riho ,  Kazuhiko Kajigaya

    发明人： Yoshiro Riho ,  Kazuhiko Kajigaya

    IPC分类号： G11C7/00

    CPC分类号： G11C11/40618 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622

    摘要： A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, comprising: a step for dividing the memory array into a holding area used as a copy source which includes memory cells on a predetermined number of word lines, and a copy area used as a copy destination which includes memory cells on word lines to which entire data of the holding area is to be copied, a step for executing copy operation in which data of each memory cell of the holding area is copied to one or more memory cells in the copy area on the same bit line or the same pair of bit lines before executing the self-refresh operation, and a step for executing the self-refresh operation in which a row address of the holding area is designated and a corresponding word line is selected and driven, and at the same time, one or more word lines in the copy area corresponding to the selected word line are selected and driven.

    摘要翻译： 一种半导体存储器件的刷新控制方法，其控制自刷新操作以将数据保持在具有多个存储单元的存储器阵列中，所述存储器阵列具有多个存储单元，所述多个存储单元位于与行地址对应的字线和与列地址对应的位线的交点处， 用于将存储器阵列分割成用作复制源的保持区域的步骤，所述保持区域包括预定数量的字线上的存储器单元，以及用作复制目的地的复制区域，所述复制目的地包括在保持的整个数据的字线上的存储单元 区域被复制，执行复制操作的步骤，其中保持区域的每个存储单元的数据被复制到同一位线或同一对位线上的复制区域中的一个或多个存储器单元，然后执行 自刷新操作，以及执行其中指定了保持区域的行地址并选择并驱动相应字线的自刷新操作的步骤，并且在第 同时，选择并驱动与所选字线对应的复制区域中的一个或多个字线。

    SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD INCLUDING REDUNDANT BIT LINE PROVIDED TO REPLACE DEFECTIVE BIT LINE 有权
    半导体器件和方法，包括提供更换缺陷位线的冗余位线

    公开(公告)号：US20140140155A1

    公开(公告)日：2014-05-22

    申请号：US14163368

    申请日：2014-01-24

    申请人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    发明人： Yoshiro Riho ,  Yoshio Mizukane ,  Hiromasa Noda

    IPC分类号： G11C29/00

    CPC分类号： G11C29/785 ,  G11C11/406 ,  G11C29/783 ,  G11C29/808 ,  G11C29/83

    摘要： A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.

    摘要翻译： 一种方法包括：基于行地址选择包括在多个存储器阵列之一中的字线，其中多个存储器阵列中的每一个包括多个字线，多个位线和冗余位线，选择 基于列地址包括在所选择的存储器存储器中的位线之一，响应于列地址，由列浮动电路选择冗余位线来代替要选择的位线中的一个位置 所述列地址指示缺陷地址，当响应于第一命令提供所述行地址时激活所述列浮动电路，以及当响应于第二命令提供所述行地址时，使所述列浮动电路失活。