Powered tailgate system
    1.
    发明授权
    Powered tailgate system 失效
    动力尾门系统

    公开(公告)号:US07159927B2

    公开(公告)日:2007-01-09

    申请号:US10887204

    申请日:2004-07-08

    IPC分类号: B60J5/10

    摘要: A powered tailgate system in which a direct driven rack 44 is connected to one end of a rod 52, one end of a curved arm 54 is connected to the other end of the rod 52, the other end of the curved arm 54 is connected to a tailgate 15, an arm side slider portion 60 which curves concentrically with the curved arm 54 is provided on the curved arm 54, and a plurality of load receiving portions 87 to 90 adapted to be brought into sliding contact with the arm side slider portion 60 so as to receive a load are disposed on a vehicle body side at intervals along a traveling direction of the curved arm 54.

    摘要翻译: 一种动力尾门系统,其中直接从动齿条44连接到杆52的一端,弯曲臂54的一端连接到杆52的另一端,弯臂54的另一端连接到 在弯曲臂54上设置有尾板15,与弯曲臂54同心地弯曲的臂侧滑块部60,并且多个负载承受部87〜90适于与臂侧滑块部60滑动接触 以沿着弯曲臂54的行进方向间隔地设置在车体侧的载荷。

    Powered tailgate system
    2.
    发明申请
    Powered tailgate system 失效
    动力尾门系统

    公开(公告)号:US20050017539A1

    公开(公告)日:2005-01-27

    申请号:US10887204

    申请日:2004-07-08

    IPC分类号: B60J5/10 E05F15/12

    摘要: A powered tailgate system in which a direct driven rack 44 is connected to one end of a rod 52, one end of a curved arm 54 is connected to the other end of the rod 52, the other end of the curved arm 54 is connected to a tailgate 15, an arm side slider portion 60 which curves concentrically with the curved arm 54 is provided on the curved arm 54, and a plurality of load receiving portions 87 to 90 adapted to be brought into sliding contact with the arm side slider portion 60 so as to receive a load are disposed on a vehicle body side at intervals along a traveling direction of the curved arm 54.

    摘要翻译: 一种动力尾门系统,其中直接从动齿条44连接到杆52的一端,弯曲臂54的一端连接到杆52的另一端,弯臂54的另一端连接到 在弯曲臂54上设置有尾板15,与弯曲臂54同心地弯曲的臂侧滑块部60,并且多个负载承受部87〜90适于与臂侧滑块部60滑动接触 以沿着弯曲臂54的行进方向间隔地设置在车体侧的载荷。

    Voltage generation circuit and semiconductor integrated circuit device
    3.
    发明申请
    Voltage generation circuit and semiconductor integrated circuit device 审中-公开
    电压发生电路和半导体集成电路器件

    公开(公告)号:US20070164809A1

    公开(公告)日:2007-07-19

    申请号:US10584395

    申请日:2004-12-02

    IPC分类号: G05F1/10

    CPC分类号: G05F3/30

    摘要: A constant current is formed by supplying voltage differences between bases and emitters of a first transistor which allows a first current to flow in the emitter thereof and a second transistor which allows a second current having a current density larger than a current density of the first transistor to flow in an emitter thereof to a first resistance. A second resistance is provided on a ground potential side of a circuit in series with the first resistance. A third and a fourth resistances are provided between collectors and the power supply voltages of the first transistor and the second transistor. Both collector voltages of the first and second transistors are supplied to a differential amplifier circuit having the CMOS constitution thus forming an output voltage and, at the same time, the output voltage is supplied to bases of the first transistor and the second transistor in common.

    摘要翻译: 通过提供允许第一电流在其发射极中流动的第一晶体管的基极和发射极之间的电压差而形成恒定电流,以及第二晶体管,其允许具有大于第一晶体管的电流密度的电流密度的第二电流 在其发射体中流动到第一阻力。 在与第一电阻串联的电路的地电位侧设置第二电阻。 集电器和第一晶体管和第二晶体管的电源电压之间提供第三和第四电阻。 第一和第二晶体管的集电极电压都被提供给具有CMOS结构的差分放大器电路,从而形成输出电压,并且同时将输出电压共同地提供给第一晶体管和第二晶体管的基极。

    UNBAKED CHINESE DUMPLINGS, BAKED CHINESE DUMPLINGS AND PROCESS FOR PRODUCING THE SAME
    4.
    发明申请
    UNBAKED CHINESE DUMPLINGS, BAKED CHINESE DUMPLINGS AND PROCESS FOR PRODUCING THE SAME 审中-公开
    中国废弃物,中国废弃物及其生产工艺

    公开(公告)号:US20090068319A1

    公开(公告)日:2009-03-12

    申请号:US12269602

    申请日:2008-11-12

    摘要: The present invention provides fried Chinese dumplings, such as fried jiao-zi, shao-mai, won-ton, and steamed bread, unfried Chinese dumplings, and methods for producing the same, wherein deterioration of the crispness of their browned skin is sufficiently inhibited after the dumplings are fried, even when a certain period of time is passed after frying, or even when the dumplings are stored in a frozen state. The unfried Chinese dumpling of the present invention has a crispness deterioration inhibitor provided on the external surface of the dough sheet for inhibiting deterioration with time of crispness of the dough sheet after the dumpling is fried. The inhibitor comprising grain powders and a starch hydrolysate (A-1) in powder form having a bulk density of not lower than 3.0 ml/g.

    摘要翻译: 本发明提供油炸饺子,蜀麦,馄饨,馒头,不中华饺子等煎炸饺子及其生产方法,充分抑制其褐色皮肤脆性的降低 饺子油炸后,即使在油炸后经过一段时间,甚至在饺子以冻结状态储存时也是如此。 本发明的未煮熟的中国饺子具有脆性劣化抑制剂,其设置在面片的外表面上,用于在饺子煎炸后抑制面片的脆性随时间变化。 所述抑制剂包含粉末形式和淀粉密度不低于3.0ml / g的粉末状淀粉水解物(A-1)。

    Semiconductor integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US07391354B2

    公开(公告)日:2008-06-24

    申请号:US11657485

    申请日:2007-01-25

    IPC分类号: H03M1/12

    摘要: One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter configured as a sub DAC that causes a DC current to flow therethrough is coupled to a second external terminal of the IC.

    摘要翻译: 分别耦合到配置为主DAC的电容阵列型D / A转换器的电容器的开关的一个输入端子耦合到IC的第一外部端子。 另一方面,构成为使DC电流流过的副DAC的电阻串型D / A转换器的电流开关型D / A转换器与IC的第二外部端子耦合。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    6.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号:US20090140802A1

    公开(公告)日:2009-06-04

    申请号:US12277465

    申请日:2008-11-25

    IPC分类号: H03F1/08

    摘要: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (−) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.

    摘要翻译: 本发明旨在减少由于采样电路中的运算放大器的输入失调电压或耦合到A / D转换器的输入端的多路复用器而提供给输入端的模拟输入信号电压的信号源阻抗中的偏移误差电压, D转换器。 半导体集成电路具有A / D转换器和采样电路。 采样电路在第一和第二采样模式下采样模拟输入信号。 A / D转换器将采样的模拟信号转换为转换模式下的数字信号。 通过在第一和第二采样模式之间切换运算放大器的内部电路,切换由第一和第二输入端实现的非反相输入端(+)和反相输入端( - )的功能。 与切换同步,切换由输入开关向同相输入端子提供模拟信号。

    Semiconductor integrated circuit and method of operating the same
    8.
    发明授权
    Semiconductor integrated circuit and method of operating the same 有权
    半导体集成电路及其操作方法

    公开(公告)号:US08525712B2

    公开(公告)日:2013-09-03

    申请号:US13195144

    申请日:2011-08-01

    IPC分类号: H03M1/10

    摘要: To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction.

    摘要翻译: 通过在安装在车载毫米波雷达装置中的半导体集成电路中减小内置A / D转换器的芯片所占用的面积来提高内置A / D转换器的分辨率, A / D转换器和MPU。 在半导体集成电路中,由单个数字校正型A / D转换器对雷达装置的多个接收信号进行A / D转换。 单个A / D转换器的数字校正型A / D转换器是从接收接口的多路复用器输出的接收信号顺序进行A / D转换的前景数字校正型A / D转换器。 单个A / D转换器包括具有多个级联耦合转换器的流水线型A / D转换器。 半导体集成电路包括校正信号生成单元,数字校正D / A转换器和用于数字校正的数字校正单元。

    Semiconductor integrated circuit
    9.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号:US07746253B2

    公开(公告)日:2010-06-29

    申请号:US12277465

    申请日:2008-11-25

    IPC分类号: H03M1/00 H03M1/12

    摘要: The present invention is directed to reduce offset error voltage in a signal source impedance of analog input signal voltage supplied to an input terminal due to input offset voltage of an operational amplifier in a sampling circuit or a multiplexer coupled to an input terminal of an A/D converter. A semiconductor integrated circuit has an A/D converter and a sampling circuit. The sampling circuit samples an analog input signal in first and second sample modes. The A/D converter converts the sampled analog signal to a digital signal in a conversion mode. By switching of an internal circuit of an operational amplifier between the first and second sample modes, the functions of a non-inverting input terminal (+) and an inverting input terminal (−) realized by first and second input terminals are switched. Synchronously with the switching, supply of an analog signal to the non-inverting input terminal by input switches is also switched.

    摘要翻译: 本发明旨在减少由于采样电路中的运算放大器的输入失调电压或耦合到A / D转换器的输入端的多路复用器而提供给输入端的模拟输入信号电压的信号源阻抗中的偏移误差电压, D转换器。 半导体集成电路具有A / D转换器和采样电路。 采样电路在第一和第二采样模式下采样模拟输入信号。 A / D转换器将采样的模拟信号转换为转换模式下的数字信号。 通过在第一和第二采样模式之间切换运算放大器的内部电路,切换由第一和第二输入端实现的非反相输入端(+)和反相输入端( - )的功能。 与切换同步,切换由输入开关向同相输入端子提供模拟信号。

    Semiconductor integrated circuit
    10.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号:US20070216558A1

    公开(公告)日:2007-09-20

    申请号:US11657485

    申请日:2007-01-25

    IPC分类号: H03M1/66

    摘要: One input terminals of switches respectively coupled to capacitors of a capacitance array type D/A converter configured as a main DAC are coupled to a first external terminal of an IC. On the other hand, a current switching type D/A converter of a resistance string type D/A converter configured as a sub DAC that causes a DC current to flow therethrough is coupled to a second external terminal of the IC.

    摘要翻译: 分别耦合到配置为主DAC的电容阵列型D / A转换器的电容器的开关的一个输入端子耦合到IC的第一外部端子。 另一方面,构成为使DC电流流过的副DAC的电阻串型D / A转换器的电流开关型D / A转换器与IC的第二外部端子耦合。