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    Method of controlled low-k via etch for Cu interconnections
    4.
    发明授权
    Method of controlled low-k via etch for Cu interconnections 有权
    用于Cu互连的受控低k通孔蚀刻的方法

    公开(公告)号：US07906426B2

    公开(公告)日：2011-03-15

    申请号：US11788969

    申请日：2007-04-23

    申请人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    发明人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

    摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

    摘要翻译： 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein
    6.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein 有权
    形成具有离子固化电绝缘层的集成电路器件的方法

    公开(公告)号：US20090098706A1

    公开(公告)日：2009-04-16

    申请号：US11871602

    申请日：2007-10-12

    申请人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    发明人： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

    IPC分类号： H01L21/762

    CPC分类号： H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

    摘要： Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

    摘要翻译： 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

    SEMICONDUCTOR PROCESSING SYSTEM WITH ULTRA LOW-K DIELECTRIC
    7.
    发明申请
    SEMICONDUCTOR PROCESSING SYSTEM WITH ULTRA LOW-K DIELECTRIC 有权
    具有超低K电介质的半导体处理系统

    公开(公告)号：US20080145795A1

    公开(公告)日：2008-06-19

    申请号：US11613155

    申请日：2006-12-19

    申请人： Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

    发明人： Yasri Yudhistira ,  Johnny Widodo ,  Bei Chao Zhang ,  Liang-Choo Hsia

    IPC分类号： G03F7/00

    CPC分类号： G03F7/0035 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

    摘要： A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region of the ultra low-K dielectric layer, evaporating the porogens from a second region of the ultra low-K dielectric layer by projecting the incoming radiation on the second region, and removing the ultra low-K dielectric layer in the first region with a developer.

    摘要翻译： 提供了一种具有超低K电介质的半导体处理系统，包括提供具有电子电路的衬底，在衬底上形成具有致孔剂的超低K电介质层，阻挡来自超低K电介质的第一区域的入射辐射， K电介质层，通过将入射辐射投射在第二区域上，从超低K电介质层的第二区域蒸发致孔剂，并用显影剂除去第一区域中的超低K电介质层。

    Capacitor top plate over source/drain to form a 1T memory device
    8.
    发明授权
    Capacitor top plate over source/drain to form a 1T memory device 有权
    源极/漏极上的电容器顶板形成1T存储器件

    公开(公告)号：US08716081B2

    公开(公告)日：2014-05-06

    申请号：US11686475

    申请日：2007-03-15

    申请人： Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

    发明人： Lee Wee Teo ,  Yong Meng Lee ,  Zhao Lun ,  Chung Woh Lai ,  Shyue Seng Tan ,  Jeffrey Chee ,  Shailendra Mishra ,  Johnny Widodo

    IPC分类号： H01L29/76

    CPC分类号： H01L29/94 ,  H01L27/10805 ,  H01L27/1085 ,  H01L27/11

    摘要： A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.

    摘要翻译： 用于诸如1T-SRAM的存储器件的方法和结构，其具有直接在掺杂底板区域上方的电容器顶板。 示例设备包括以下。 形成为围绕衬底上的有源区域的隔离膜。 形成在有源区域的一部分上的栅极电介质和栅电极。 与栅电极相邻的衬底中的源极元件和漏极元件。 漏极元件由漏区和底板区组成。 漏极区域位于底板区域和栅极结构之间。 电容器电介质和电容器顶板在底板区域的至少部分上方。

    Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls
    10.
    发明申请
    Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls 有权
    在形成连续侧壁的绝缘层内形成电气互连的方法

    公开(公告)号：US20090239369A1

    公开(公告)日：2009-09-24

    申请号：US12051223

    申请日：2008-03-19

    申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    IPC分类号： H01L21/31 ,  H01L21/44

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

    摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

    摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。