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28 条记录 (耗时 0.023 秒)

    Eight transistor SRAM cell with improved stability requiring only one word line
    1.
    发明申请
    Eight transistor SRAM cell with improved stability requiring only one word line 有权
    八个晶体管SRAM单元具有改进的稳定性，只需要一个字线

    公开(公告)号：US20070165445A1

    公开(公告)日：2007-07-19

    申请号：US11334647

    申请日：2006-01-18

    申请人： Yuen Chan ,  William Huott ,  Donald Plass

    发明人： Yuen Chan ,  William Huott ,  Donald Plass

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C8/14

    摘要： An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

    摘要翻译： 由单个字线访问的SRAM单元和用于读取和写入操作的单独的存取晶体管。 一对写位线传输器件分别提供用于写操作的交叉耦合上拉，下拉晶体管对的右侧和左侧的访问以及与字线晶体管串联的单个读取位线晶体管，当 选中，读取单元格的内容。

    Integrated circuit chip with improved array stability
    2.
    发明申请
    Integrated circuit chip with improved array stability 失效
    集成电路芯片具有改进的阵列稳定性

    公开(公告)号：US20050063232A1

    公开(公告)日：2005-03-24

    申请号：US10950940

    申请日：2004-09-27

    申请人： Yuen Chan ,  Rajiv Joshi ,  Donald Plass

    发明人： Yuen Chan ,  Rajiv Joshi ,  Donald Plass

    IPC分类号： G11C5/06 ,  G11C8/08 ,  G11C11/00 ,  G11C11/413

    CPC分类号： G11C8/08 ,  G11C11/412 ,  G11C11/417

    摘要： A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

    摘要翻译： 可以由多个电源提供的多阈值集成电路（IC），具有诸如阵列静态随机存取存储器（SRAM）单元的锁存器阵列和具有改进的稳定性和减小的亚阈值泄漏的CMOS SRAM。 阵列单元中的选定器件（NFET和/或PFET）和支持逻辑，例如在数据通路和非关键逻辑中，都适用于较低的栅极和亚阈值泄漏。 正常基极FET具有基极阈值，并且定制的FET具有高于阈值。 在多电源芯片中，具有定制FET的电路由增加的电源电压供电。

    SRAM array with improved cell stability
    3.
    发明申请
    SRAM array with improved cell stability 有权
    具有改善电池稳定性的SRAM阵列

    公开(公告)号：US20050078508A1

    公开(公告)日：2005-04-14

    申请号：US10950928

    申请日：2004-09-27

    申请人： Yuen Chan ,  Rajiv Joshi ,  Donald Plass

    发明人： Yuen Chan ,  Rajiv Joshi ,  Donald Plass

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413 ,  G11C8/08

    摘要： A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability

    摘要翻译： CMOS静态随机存取存储器（SRAM）单元阵列，包括该阵列的集成芯片以及一种以更好的单元稳定性访问阵列中的单元的方法。 连接到阵列中的一半选定单元的位线在单元访问期间浮动以改善单元稳定性

    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE
    4.
    发明申请
    MULTIFUNCTIONAL LATCH CIRCUIT FOR USE WITH BOTH SRAM ARRAY AND SELF TEST DEVICE 失效
    具有两个SRAM阵列和自检测试器件的多功能锁存电路

    公开(公告)号：US20060176731A1

    公开(公告)日：2006-08-10

    申请号：US11055043

    申请日：2005-02-10

    申请人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    发明人： Andrew Bianchi ,  Yuen Chan ,  William Huott ,  Michael Hyeok Lee ,  Edelmar Seewann ,  Philip Shephard

    IPC分类号： G11C11/00

    CPC分类号： G11C29/1201 ,  G11C11/41 ,  G11C11/419 ,  G11C29/12

    摘要： An apparatus and method is provided that combines both self test and functional features in a single latch circuit, which may be used with an SRAM array and is usefully embodied as an L1-L2 latch. During partial writes from an SRAM array, data bits of unknown state are inhibited from entering the latch circuit, while data for testing is allowed to enter. In one useful embodiment of the invention the latch circuit is used with a mode control that provides mode select signals to operate the latch circuit in one of a plurality of modes, including at least full write and partial write modes. The latch circuit further includes a data hold circuit for selectively receiving and storing data coupled to the latch circuit. A first enabling circuit responsive to the mode select signals enables the hold circuit to receive all the data contained in the array during a full write mode, and further enables the hold circuit to receive only some of the data bits contained in the array during a partial write mode, while preventing other data bits of “X” state from entering the latch circuit. A second enabling circuit enables the data hold circuit to receive data bits from a self test source in place of respective data bits from the SRAM array that are prevented from entering the latch circuit.

    摘要翻译： 提供了将单个锁存电路中的自检和功能特征组合在一起的装置和方法，其可以与SRAM阵列一起使用，并且被有效地实现为L 1 -L 2锁存器。 在从SRAM阵列的部分写入期间，未知状态的数据位被禁止进入锁存电路，而用于测试的数据被允许进入。 在本发明的一个有用的实施例中，锁存电路与提供模式选择信号的模式控制一起使用，以便以至少全写和部分写模式的多种模式之一来操作锁存电路。 锁存电路还包括数据保持电路，用于选择性地接收和存储耦合到锁存电路的数据。 响应于模式选择信号的第一使能电路使得保持电路能够在完全写入模式期间接收包含在阵列中的所有数据，并且还允许保持电路仅在部分时钟期间仅接收阵列中包含的一些数据位 写模式，同时防止“X”状态的其他数据位进入锁存电路。 第二启用电路使得数据保持电路能够从自检源代替来自SRAM阵列的相应数据位，以防止其进入锁存电路。

    RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE
    7.
    发明申请
    RING OSCILLATOR ROW CIRCUIT FOR EVALUATING MEMORY CELL PERFORMANCE 失效
    用于评估存储器单元性能的振荡器振荡器电路

    公开(公告)号：US20080094878A1

    公开(公告)日：2008-04-24

    申请号：US11963794

    申请日：2007-12-22

    申请人： Rajiv Joshi ,  Qiuyi Ye ,  Yuen Chan ,  Anirudh Devgan

    发明人： Rajiv Joshi ,  Qiuyi Ye ,  Yuen Chan ,  Anirudh Devgan

    IPC分类号： G11C11/00

    CPC分类号： G11C29/50 ,  G11C29/50012

    摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

    摘要翻译： 用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。 环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

    System and method of assessing reliability of a semiconductor
    8.
    发明申请
    System and method of assessing reliability of a semiconductor 审中-公开
    评估半导体可靠性的系统和方法

    公开(公告)号：US20080016486A1

    公开(公告)日：2008-01-17

    申请号：US11417451

    申请日：2006-05-03

    申请人： Yuen Chan ,  Yong Han Low ,  Yue Huang ,  Kok Goh ,  Kok Tan

    发明人： Yuen Chan ,  Yong Han Low ,  Yue Huang ,  Kok Goh ,  Kok Tan

    IPC分类号： G06F17/50 ,  H03K19/00 ,  H01L21/66 ,  G01R31/26

    CPC分类号： G06F17/5045 ,  G06F17/504

    摘要： A system for assessing reliability of a semiconductor product design, the system comprising a first database for storing circuits data specifying cells of available circuits for semiconductor products; an input unit for input of reliability qualification data of tested semiconductor products; an uploading unit for uploading semiconductor product design data; and a processor for processing the reliability qualification data to generate reliability data at a circuit-level, a cell-level, or both utilizing the circuits data, and for assessing the reliability of the semiconductor product design based on the generated reliability data.

    摘要翻译： 一种用于评估半导体产品设计的可靠性的系统，所述系统包括：第一数据库，用于存储指定用于半导体产品的可用电路单元的电路数据; 用于输入测试半导体产品的可靠性鉴定数据的输入单元; 用于上传半导体产品设计数据的上传单元; 以及处理器，用于处理可靠性鉴定数据，以便利用电路数据在电路级，单元级或两者产生可靠性数据，以及基于所生成的可靠性数据来评估半导体产品设计的可靠性。