公开(公告)号：US08536706B2

公开(公告)日：2013-09-17

申请号：US13707359

申请日：2012-12-06

申请人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

公开(公告)号：US08344509B2

公开(公告)日：2013-01-01

申请号：US12652204

申请日：2010-01-05

申请人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi Hayashi ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20100181673A1

公开(公告)日：2010-07-22

申请号：US12652204

申请日：2010-01-05

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20130093090A1

公开(公告)日：2013-04-18

申请号：US13707359

申请日：2012-12-06

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US08648464B2

公开(公告)日：2014-02-11

申请号：US13413854

申请日：2012-03-07

申请人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

发明人： Masayuki Kitamura ,  Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naoshi Sakuma ,  Ichiro Mizushima

IPC分类号： H01L23/48

CPC分类号： H01L21/02639 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/02527 ,  H01L21/02645 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53276 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device is disclosed. The device includes a semiconductor substrate, and an interconnection above the semiconductor substrate. The interconnection includes a co-catalyst layer, a catalyst layer on the co-catalyst layer, and a graphene layer on the catalyst layer. The co-catalyst layer includes a portion contacting the catalyst layer. The portion has a face-centered cubic structure with a (111) plane oriented parallel to a surface of the semiconductor substrate. The catalyst layer has a face-centered cubic structure with a (111) plane oriented parallel to the surface of the semiconductor substrate.

摘要翻译： 根据一个实施例，公开了一种半导体器件。 该器件包括半导体衬底和半导体衬底上方的互连。 互连包括助催化剂层，助催化剂层上的催化剂层和催化剂层上的石墨烯层。 助催化剂层包括与催化剂层接触的部分。 该部分具有面平面立方结构，其中（111）面平行于半导体衬底的表面定向。 催化剂层具有面平面立方结构，其中（111）面平行于半导体衬底的表面取向。

公开(公告)号：US08482126B2

公开(公告)日：2013-07-09

申请号：US13224929

申请日：2011-09-02

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L23/53276 ,  H01L21/28556 ,  H01L21/76805 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.

摘要翻译： 根据本发明的实施例，一种装置包括基板，形成在基板上或上方的基体，以及一对布线。 基体在平面图中具有线状并沿长度方向延伸。 一对配线包括在基体的长度方向上形成在基体的两侧面上的第一和第二催化剂层，夹着基体; 以及分别以与基体的长度方向接触的方式形成在基体的两侧面上的第一和第二石墨烯层，所述石墨烯层包括垂直层叠的多个石墨烯层 分别相对于基体的两个侧面。

公开(公告)号：US20120080661A1

公开(公告)日：2012-04-05

申请号：US13216435

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L29/15 ,  H01L21/441

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

摘要翻译： 根据一个实施例，石墨烯互连包括绝缘膜，催化剂膜和石墨烯层。 绝缘膜包括互连沟槽。 在互连沟槽中形成催化剂膜并填充互连沟槽的至少一部分。 在互连沟槽中的催化剂膜上形成石墨烯层，并且包括沿垂直于互连沟槽的底表面的方向堆叠的石墨烯片。

公开(公告)号：US20120049370A1

公开(公告)日：2012-03-01

申请号：US13215463

申请日：2011-08-23

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

IPC分类号： H01L23/522 ,  H01L21/768 ,  B82Y99/00

CPC分类号： H01L23/53276 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.

摘要翻译： 根据一个实施例，碳纳米管互连包括第一导电层，绝缘膜，底层催化剂，催化剂失活膜，催化剂膜和碳纳米管。 绝缘膜形成在第一导电层上并包括孔。 在孔的底面上的第一导电层和孔的侧面的绝缘膜上形成催化剂底膜。 在孔中的侧表面上的催化剂底层上形成催化剂失活膜。 在孔的底面的催化剂底层和孔的侧面的催化剂失活膜上形成催化剂膜。 在孔中形成碳纳米管，碳纳米管包括与孔中底表面上的催化剂膜接触的一端。

公开(公告)号：US09159615B2

公开(公告)日：2015-10-13

申请号：US13216435

申请日：2011-08-24

申请人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

发明人： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

摘要翻译： 根据一个实施例，石墨烯互连包括绝缘膜，催化剂膜和石墨烯层。 绝缘膜包括互连沟槽。 在互连沟槽中形成催化剂膜并填充互连沟槽的至少一部分。 在互连沟槽中的催化剂膜上形成石墨烯层，并且包括沿垂直于互连沟槽的底表面的方向堆叠的石墨烯片。

公开(公告)号：US08487449B2

公开(公告)日：2013-07-16

申请号：US13215463

申请日：2011-08-23

申请人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

发明人： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

IPC分类号： H01L29/70 ,  H01L21/4763

CPC分类号： H01L23/53276 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.

摘要翻译： 根据一个实施例，碳纳米管互连包括第一导电层，绝缘膜，底层催化剂，催化剂失活膜，催化剂膜和碳纳米管。 绝缘膜形成在第一导电层上并包括孔。 在孔的底面上的第一导电层和孔的侧面的绝缘膜上形成催化剂底膜。 在孔中的侧表面上的催化剂底层上形成催化剂失活膜。 在孔的底面的催化剂底层和孔的侧面的催化剂失活膜上形成催化剂膜。 在孔中形成碳纳米管，碳纳米管包括与孔中底表面上的催化剂膜接触的一端。