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公开(公告)号:US20090209050A1
公开(公告)日:2009-08-20
申请号:US12032973
申请日:2008-02-18
申请人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
发明人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
IPC分类号: H01L21/00
CPC分类号: H01L27/228 , G11C11/161 , G11C11/1657 , G11C11/1659 , H01L43/08 , H01L43/12
摘要: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.
摘要翻译: 形成集成电路的方法包括形成磁隧道结(MTJ)层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层,其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。
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公开(公告)号:US08143683B2
公开(公告)日:2012-03-27
申请号:US12756743
申请日:2010-04-08
申请人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
发明人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
IPC分类号: H01L29/82
CPC分类号: H01L27/228 , G11C11/161 , G11C11/1657 , G11C11/1659 , H01L43/08 , H01L43/12
摘要: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.
摘要翻译: 形成集成电路的方法包括形成磁隧道结(MTJ)层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层,其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。
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公开(公告)号:US20100193891A1
公开(公告)日:2010-08-05
申请号:US12756743
申请日:2010-04-08
申请人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
发明人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
IPC分类号: H01L29/82
CPC分类号: H01L27/228 , G11C11/161 , G11C11/1657 , G11C11/1659 , H01L43/08 , H01L43/12
摘要: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.
摘要翻译: 形成集成电路的方法包括形成磁隧道结(MTJ)层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层,其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。
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公开(公告)号:US07723128B2
公开(公告)日:2010-05-25
申请号:US12032973
申请日:2008-02-18
申请人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
发明人: Yung-Hung Wang , Yu-Jen Wang , Mark Juang , Chia-Shiung Tsai
IPC分类号: H01L21/00
CPC分类号: H01L27/228 , G11C11/161 , G11C11/1657 , G11C11/1659 , H01L43/08 , H01L43/12
摘要: A method of forming an integrated circuit includes forming magnetic tunnel junction (MTJ) layers; etching the MTJ layers to form a MTJ cell; and forming a dielectric capping layer on sidewalls of the MTJ cell, wherein the step of forming the dielectric capping layer is in-situ performed with the step of etching the MTJ layers.
摘要翻译: 形成集成电路的方法包括形成磁隧道结(MTJ)层; 蚀刻MTJ层以形成MTJ电池; 以及在MTJ电池的侧壁上形成电介质覆盖层,其中形成电介质覆盖层的步骤是用蚀刻MTJ层的步骤进行的。
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公开(公告)号:US08080471B2
公开(公告)日:2011-12-20
申请号:US12754451
申请日:2010-04-05
申请人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
发明人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
IPC分类号: H01L21/4763
CPC分类号: H01L43/12 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/08
摘要: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
摘要翻译: 这里公开了一种改进的存储器件和相关的制造方法,其中传统的着陆焊盘占据的面积显着地减少到传统的着陆焊盘占据的面积的大约50%到10%。 这是通过从电池结构中去除着陆焊盘而实现的,而是形成导电通孔结构,其提供从结构中的存储器堆或器件到下金属层的电连接。 通过仅形成该通孔结构,而不是形成在着陆焊盘的任一侧上的分离的通孔,结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小,因此通孔结构和下面 金属层可以形成为更靠近存储器堆叠(或与堆叠相关联的导体),以便减小电池结构的整体宽度。
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公开(公告)号:US07851324B2
公开(公告)日:2010-12-14
申请号:US11586528
申请日:2006-10-26
申请人: Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
发明人: Yu-Jen Wang , Chia-Shiung Tsai , Yeur-Luen Tu , Lan-Lin Chao , Chih-Ta Wu , Hsing-Lien Lin , Chung Chien Wang
IPC分类号: H01L29/94
CPC分类号: H01L28/60 , H01L21/321
摘要: A method of manufacturing a semiconductor device includes forming a metal-insulator-metal (MIM) device having a metal organic chemical vapor deposited (MOCVD) lower electrode and an atomic layer deposited (ALD) upper electrode.
摘要翻译: 一种制造半导体器件的方法包括形成具有金属有机化学气相沉积(MOCVD)下电极和原子层沉积(ALD)上电极的金属 - 绝缘体 - 金属(MIM)器件。
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公开(公告)号:US20120170358A1
公开(公告)日:2012-07-05
申请号:US13308065
申请日:2011-11-30
申请人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
发明人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
IPC分类号: G11C11/16 , H01L29/82 , H01L21/8246
CPC分类号: H01L43/12 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/08
摘要: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
摘要翻译: 这里公开了一种改进的存储器件和相关的制造方法,其中传统的着陆焊盘占据的面积显着地减少到传统的着陆焊盘占据的面积的大约50%到10%。 这是通过从电池结构中移除着陆焊盘而实现的,而是形成导电通孔结构,其提供从结构中的存储器堆或器件到下金属层的电连接。 通过仅形成该通孔结构,而不是形成在着陆焊盘的任一侧上的分离的通孔,结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小,因此通孔结构和下面 金属层可以形成为更靠近存储器堆叠(或与堆叠相关联的导体),以便减小电池结构的整体宽度。
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公开(公告)号:US07692230B2
公开(公告)日:2010-04-06
申请号:US11674581
申请日:2007-02-13
申请人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
发明人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
IPC分类号: H01L27/108
CPC分类号: H01L43/12 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/08
摘要: Disclosed herein is an improved memory device wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
摘要翻译: 这里公开了一种改进的存储装置,其中由常规着陆垫占据的面积显着地减小到常规着陆垫占据的面积的大约50%至10%。 这是通过从电池结构中移除着陆焊盘而实现的,而是形成导电通孔结构,其提供从结构中的存储器堆或器件到下金属层的电连接。 通过仅形成该通孔结构,而不是形成在着陆焊盘的任一侧上的分离的通孔,结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小,因此通孔结构和下面 金属层可以形成为更靠近存储器堆叠(或与堆叠相关联的导体),以便减小电池结构的整体宽度。
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公开(公告)号:US08889507B2
公开(公告)日:2014-11-18
申请号:US11765971
申请日:2007-06-20
申请人: Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
发明人: Chih-Ta Wu , Jason Lee , Chung Chien Wang , Hsing-Lien Lin , Yu-Jen Wang , Yeur-Luen Tu , Chern-Yow Hsu , Yuan-Hung Liu , Chi-Hsin Lo , Chia-Shiung Tsai , Lucy Chang , Chia-Lin Chen , Ming-Chih Tsai
IPC分类号: H01L21/8234 , H01L21/8244 , H01L49/02 , H01L27/108
CPC分类号: H01L27/10814 , H01L27/10852 , H01L28/40 , H01L28/75
摘要: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.
摘要翻译: 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。
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公开(公告)号:US20110143514A1
公开(公告)日:2011-06-16
申请号:US12754451
申请日:2010-04-05
申请人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
发明人: Jhon Jhy Liaw , Yu-Jen Wang , Chia-Shiung Tsai
IPC分类号: H01L21/28
CPC分类号: H01L43/12 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H01L27/228 , H01L43/08
摘要: Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.
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