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    Method of forming MIM capacitor electrodes
    5.
    发明申请
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US20050215004A1

    公开(公告)日：2005-09-29

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01G4/005 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/522 ,  H01L29/06

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Method of forming MIM capacitor electrodes
    6.
    发明授权
    Method of forming MIM capacitor electrodes 有权
    形成MIM电容器电极的方法

    公开(公告)号：US07199001B2

    公开(公告)日：2007-04-03

    申请号：US10811657

    申请日：2004-03-29

    申请人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    发明人： Chih-Ta Wu ,  Kuo-Yin Lin ,  Tsung-Hsun Huang ,  Chung-Yi Yu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Hsing-Lien Lin ,  Chia-Shiung Tsai

    IPC分类号： H01L21/8242

    CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A novel method for forming electrodes in the fabrication of an MIM (metal-insulator-metal) capacitor, is disclosed. The method improves MIM capacitor performance by preventing plasma-induced damage to a dielectric layer during deposition of a top electrode on the dielectric layer, as well as by reducing or preventing the formation of an interfacial layer between the dielectric layer and the electrode or electrodes, in fabrication of the MIM capacitor. The method typically includes the patterning of crown-type capacitor openings in a substrate; depositing a bottom electrode in each of the crown openings; subjecting the bottom electrode to a rapid thermal processing (RTP) or furnace anneal step; depositing a dielectric layer on the annealed bottom electrode; depositing a top electrode on the dielectric layer using a plasma-free CVD (chemical vapor deposition) or ALD (atomic layer deposition) process; and patterning the top electrode of each MIM capacitor.

    摘要翻译： 公开了一种用于在MIM（金属 - 绝缘体 - 金属）电容器的制造中形成电极的新颖方法。 该方法通过在电介质层上的顶部电极沉积期间防止等离子体对电介质层的损伤，以及通过减少或防止介电层和电极或电极之间的界面层的形成来改善MIM电容器性能， 在MIM电容器的制造中。 该方法通常包括在衬底中图案化冠状电容器开口; 在每个冠状开口中沉积底部电极; 对底部电极进行快速热处理（RTP）或炉退火步骤; 在退火的底部电极上沉​​积介电层; 使用无等离子体CVD（化学气相沉积）或ALD（原子层沉积）工艺在电介质层上沉积顶部电极; 并对每个MIM电容器的顶部电极进行构图。

    Low tunneling current MIM structure and method of manufacturing same
    7.
    发明申请
    Low tunneling current MIM structure and method of manufacturing same 有权
    低隧道电流MIM结构及其制造方法

    公开(公告)号：US20070247784A1

    公开(公告)日：2007-10-25

    申请号：US11379478

    申请日：2006-04-20

    申请人： Yu-Jen Wang ,  Hsing-Lien Lin ,  Yeur-Luen Tu

    发明人： Yu-Jen Wang ,  Hsing-Lien Lin ,  Yeur-Luen Tu

    IPC分类号： H01G4/06

    CPC分类号： H01G4/10 ,  H01G4/005 ,  H01G4/12 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

    摘要翻译： 这里公开了具有增加的电容，很少或没有隧道电流的新的MIM结构，以及相关的制造方法。 在一个实施例中，新的MIM结构包括包括磁性金属并且具有在第一方向上对准的磁矩的第一电极和包括磁性金属的第二电极，并且具有在与第一方向相反的第二方向上对准的磁矩 。 此外，这种MIM结构包括形成在第一和第二电极之间并与第一和第二磁性金属接触的电介质层。

    Low tunneling current MIM structure and method of manufacturing same
    8.
    发明授权
    Low tunneling current MIM structure and method of manufacturing same 有权
    低隧道电流MIM结构及其制造方法

    公开(公告)号：US07529078B2

    公开(公告)日：2009-05-05

    申请号：US11379478

    申请日：2006-04-20

    申请人： Yu-Jen Wang ,  Hsing-Lien Lin ,  Yeur-Luen Tu

    发明人： Yu-Jen Wang ,  Hsing-Lien Lin ,  Yeur-Luen Tu

    IPC分类号： H01G4/38

    CPC分类号： H01G4/10 ,  H01G4/005 ,  H01G4/12 ,  H01G4/33 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

    摘要翻译： 这里公开了具有增加的电容，很少或没有隧道电流的新的MIM结构，以及相关的制造方法。 在一个实施例中，新的MIM结构包括包括磁性金属并且具有在第一方向上对准的磁矩的第一电极和包括磁性金属的第二电极，并且具有在与第一方向相反的第二方向上对准的磁矩 。 此外，这种MIM结构包括形成在第一和第二电极之间并与第一和第二磁性金属接触的电介质层。

    Passivation layer etching process for memory arrays with fusible links
    10.
    发明授权
    Passivation layer etching process for memory arrays with fusible links 有权
    具有可熔链接的存储器阵列的钝化层蚀刻工艺

    公开(公告)号：US06180503B2

    公开(公告)日：2001-01-30

    申请号：US09354852

    申请日：1999-07-29

    申请人： Wen-Tsing Tzeng ,  Chun-Pin Yang ,  Hsing-Lien Lin

    发明人： Wen-Tsing Tzeng ,  Chun-Pin Yang ,  Hsing-Lien Lin

    IPC分类号： H01L2144

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is described for progressively forming a fuse access openings in integrated circuits which are built with redundancy and use laser trimming to remove and insert circuit sections. The fuses are formed in a polysilicon layer and covered by one or more relatively thin insulative layers. An etch stop is patterned over the fuse in a higher level polysilicon layer or a first metallization layer. Additional insulative layers such as inter-metal dielectric layers are then formed over the etch stop. A first portion of the laser access window is then etched during the via etch for the top metallization level. The etch stop prevents removal of the insulation subjacent to it. Cumulative thickness non-uniformities in the relatively thick upper insulative layers are thus removed from the fuse window. The etch stop is removed during patterning of the top level metallization. A passivation layer is applied and patterned to exposed bonding pads and, at the same time complete the etching of the laser access window to a desired thickness over the fuses. The passivation layer over etch required to penetrate the insulation layer over the fuses also removes an ARC over the bonding pads. The process fit conveniently within the framework of an existing process and does not introduce any additional steps. In addition, the passivation layer can be patterned to form final access to both bonding pads and laser access openings with a single photolithographic mask.

    摘要翻译： 描述了一种用于在集成电路中逐渐形成熔断器存取开口的方法，该集成电路用冗余构建并且使用激光修整来去除和插入电路部分。 保险丝形成在多晶硅层中并被一个或多个相对薄的绝缘层覆盖。 在较高级多晶硅层或第一金属化层上的熔丝上图案化刻蚀停止。 然后在蚀刻停止点上形成附加的绝缘层，例如金属间介电层。 然后在用于顶部金属化水平的通孔蚀刻期间蚀刻激光入口窗口的第一部分。 蚀刻停止可防止其下方的绝缘层的移除。 因此，相对较厚的上绝缘层中的累积厚度不均匀性从保险丝窗口移除。 在顶层金属化的图案化期间去除蚀刻停止。 施加钝化层并将其图案化为暴露的焊盘，并且同时完成激光接入窗口的蚀刻到熔丝上的所需厚度。 穿过保险丝上方的绝缘层所需的钝化层过蚀刻也可以通过焊盘去除ARC。 该过程在现有过程的框架内方便地配合，并且不引入任何附加步骤。 此外，钝化层可以被图案化以通过单个光刻掩模形成对键合焊盘和激光器访问开口的最终访问。