公开(公告)号：US07728745B2

公开(公告)日：2010-06-01

申请号：US12108118

申请日：2008-04-23

申请人： Yuya Shigenobu ,  Yoshiyuki Wada ,  Satoshi Yamaguchi ,  Kozo Kimura ,  Takeshi Furuta

发明人： Yuya Shigenobu ,  Yoshiyuki Wada ,  Satoshi Yamaguchi ,  Kozo Kimura ,  Takeshi Furuta

IPC分类号： H03M7/40

CPC分类号： H03M7/425

摘要： A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the extracting unit extracts the bit string to be decoded next in the same cycle as a cycle in which the judgment was made by the first judging unit, and extracts the bit string to be decoded next in a cycle following the cycle in which the judgment was made by the second judging unit.

摘要翻译： 根据本发明的可变长度码解码装置包括：提取单元，从比特流的开始提取比特串; 第一存储单元，用于存储已经编码了一条数据的多个码字，以及分别对应于码字的解码数据和码长; 第二存储单元，用于存储已编码了两个或多个数据的多个码字，以及分别对应于码字的解码数据和码长; 第一判断单元，判断存储在第一存储单元中的一个代码字是否包括在提取的位串中，并且当被判断为包括时，输出解码数据和代码字的代码长度; 以及第二判断单元，判断存储在第二存储单元中的代码字是否包括在提取的位串中，并且当被判断为包括时，输出解码数据和代码字的代码长度，其中提取单元提取 接下来要在与第一判断单元进行判断的周期相同的周期中解码的比特串，并且在第二个判断结束的周期之后的周期中提取下一个要解码的比特串 判断单位

公开(公告)号：US20090049219A1

公开(公告)日：2009-02-19

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 为了提供能够执行异常处理程序与正常处理之间的切换的信息处理装置，所述信息处理装置包括：信息处理装置，包括：处理器; 数据处理单元，用于在从所述处理器接收到处理请求时执行特定处理; 中断控制器，用于向所述处理器发出中断请求; 以及异常控制单元，其可操作以控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接，所述数据处理单元包括通知单元，用于经由所述专用线通知所述异常控制单元 表示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以执行异常处理程序 处理器。

公开(公告)号：US07934082B2

公开(公告)日：2011-04-26

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F9/48

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括处理器，数据处理单元，其在从处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中，所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器向处理器发出执行异常处理程序的中断请求。

公开(公告)号：US08082429B2

公开(公告)日：2011-12-20

申请号：US13052281

申请日：2011-03-21

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F9/48

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

公开(公告)号：US20110173361A1

公开(公告)日：2011-07-14

申请号：US13052281

申请日：2011-03-21

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括：处理器; 数据处理单元，在从所述处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器发出中断请求以对处理器执行异常处理程序。

公开(公告)号：US20080215858A1

公开(公告)日：2008-09-04

申请号：US12110539

申请日：2008-04-28

申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US20070286275A1

公开(公告)日：2007-12-13

申请号：US10599494

申请日：2005-04-01

申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

IPC分类号： H04B1/66 ,  G06F13/12

CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

摘要： The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.

摘要翻译： 本发明提供了一种用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 该集成电路包括一个包括CPU的微处理器块2，用于向外部设备输入/输出视频和音频流的流I / O块4，用于执行媒体处理的媒体处理块3，包括至少一个 输入到流I / O块4的视频和音频流等的压缩和解压缩，用于将经过媒体处理块3中的媒体处理的视频和音频流转换成视频和音频信号的AV IO块5 并将这些信号输出到外部设备等;以及存储器IF块6，用于控制微计算机块2，流I / C块4，媒体处理块3和AV IO块5之间的数据传输，以及外部 记忆9。

公开(公告)号：US07236948B1

公开(公告)日：2007-06-26

申请号：US10416723

申请日：2000-11-15

申请人： Masaaki Mochimaru ,  Makiko Kouchi ,  Kozo Kimura ,  Tsuneaki Utsumi

发明人： Masaaki Mochimaru ,  Makiko Kouchi ,  Kozo Kimura ,  Tsuneaki Utsumi

IPC分类号： G06Q30/00 ,  G06F17/30

CPC分类号： A43D1/02 ,  G01B21/20 ,  G06Q30/0621

摘要： A foot shape information distributing system for distributing foot shape information including cross section data generated based on anatomical feature points of a foot. Eleven defined cross sections (A to K) are determined and stored. Server machine distributes foot shape information including the same cross section data and the same feature points as user terminal stores. Based upon the cross sections, shoes are selected or manufactured for a customer.

摘要翻译： 一种脚形信息分发系统，用于分布脚形信息，包括基于脚的解剖特征点生成的横截面数据。 确定并存储11个定义的横截面（A至K）。 服务器机器分配包括与用户终端存储相同的横截面数据和相同特征点的脚形信息。 基于横截面，为客户选择或制造鞋子。

公开(公告)号：US06212236B1

公开(公告)日：2001-04-03

申请号：US09048190

申请日：1998-03-25

申请人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

IPC分类号： H04N712

CPC分类号： H04N19/507 ,  H04N19/61

摘要： Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.

摘要翻译： 比特流分析单元111从比特流中的每个块获取编码块模式和编码的量化DCT系数。 熵解码单元112将编码块模式解码为块模式，并将编码的量化DCT系数解码为游程长度和有效性因子对。 去量化单元115从游程长度和有效性因子的对生成正交变换系数。 逆离散余弦变换（IDCT）单元110从正交变换系数生成差分图像。 当图像为“跳过”块时，解码控制单元110指示第一选择单元118选择从第一常数生成单元117输出的常数“0”。 图像存储单元120存储已被解码的多个参考帧图像。 图像恢复单元119通过将解码的差异图像添加到从存储在图像存储单元120中的参考帧图像中读取的参考块来恢复原始块。

公开(公告)号：US6075899A

公开(公告)日：2000-06-13

申请号：US66308

申请日：1998-03-27

申请人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

发明人： Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Kozo Kimura

IPC分类号： H04N5/907 ,  H04N9/64 ,  H04N19/00 ,  H04N19/423 ,  H04N19/426 ,  H04N19/44 ,  H04N19/46 ,  H04N19/503 ,  H04N19/59 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/85 ,  H04N19/91 ,  G06K9/46

CPC分类号： H04N5/907 ,  H04N19/42 ,  H04N19/423 ,  H04N19/61 ,  H04N9/64

摘要： An image memory stores a one-screen image by dividing the one-screen image into a plurality of image blocks which are each m pixels wide by n pixels high. The image memory has an array-like storage region storing s*t first chrominance components that compose one image block and s*t second chrominance components that compose the same image block in serial areas between a start area specified by a row address and a first column address and an end area specified by the same row address and a second column address (see FIG. 10). The storage region also stores m*n luminance components that compose the same image block in serial areas between a different start area specified by a different row address and a third column address and an end area are specified by the different row address and a fourth column address.

摘要翻译： PCT No.PCT / JP97 / 02995 Sec。 371日期：1998年4月27日 102（e）日期1998年4月27日PCT 1997年8月29日PCT公布。 第WO98 / 09444号公报 日期1998年3月5日图像存储器通过将单屏图像分成多个像素宽×高n个像素的图像块来存储单屏图像。 图像存储器具有存储s * t个第一色度分量的阵列状存储区域，其构成一个图像块和s * t个第二色度分量，其在由行地址指定的起始区域和第一个 列地址和由相同行地址和第二列地址指定的结束区域（参见图10）。 存储区域还存储在由不同行地址指定的不同起始区域和第三列地址之间的串行区域中构成相同图像块的m * n个亮度分量，并且结束区域由不同的行地址和第四列 地址。