公开(公告)号：US5706463A

公开(公告)日：1998-01-06

申请号：US854418

申请日：1997-05-12

申请人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

发明人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

IPC分类号： G06F12/08

CPC分类号： G06F12/0822 ,  G06F12/0815

摘要： A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.

摘要翻译： 公开了一种多处理器计算机系统，其通过禁用用于不可能由请求处理器写入的数据的高速缓存一致性协议的第一写入优化来减少通过存储器互连的无效和复制操作的发生。 这样的数据包括只读代码段。 代码段（包括指令和数据）在多个处理器之间共享。 请求处理器在只读数据块的高速缓存未命中时生成“读取共享始终”请求，否则生成“读取共享”请求。 读共享始终请求将存储在高速缓冲存储器中的数据块中的结果标记为“共享”状态，而读共享请求导致数据块标记为“独占”状态。

公开(公告)号：US5737755A

公开(公告)日：1998-04-07

申请号：US797995

申请日：1997-02-12

申请人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

发明人： Zahir Ebrahim ,  Satyanarayana Nishtala ,  William Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0808 ,  G06F12/0817

摘要： A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

摘要翻译： 公开了一种计算机系统，其包括存储器子系统和具有外部高速缓存的处理器子系统和用于使处理器子系统中的高速缓存的数据块无效并用于减少假无效操作的外部机制。 处理器子系统向指定数据块的存储器子系统发出写入无效消息，并且包括指示数据块是否存在于外部高速缓存中的无效咨询指示。 无效咨询指示确定存储器子系统是否向处理器子系统返回无效消息以用于写入无效操作。

公开(公告)号：US5657472A

公开(公告)日：1997-08-12

申请号：US414922

申请日：1995-03-31

申请人： William C. Van Loo ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III ,  Charles E. Narad

发明人： William C. Van Loo ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III ,  Charles E. Narad

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0828

摘要： A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.

摘要翻译： 提供了具有多个子系统和耦合到系统控制器的主存储器的多处理器计算机系统。 互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。 至少两个子系统是数据处理器，每个数据处理器具有存储多个数据块的相应高速缓存存储器和相应的主高速缓存索引。 每个主缓存索引具有一组主缓存标签（Etags），包括缓存存储器存储的每个数据块的一个缓存标签。 每个数据处理器包括主界面，用于向系统控制器发送存储器事务请求，以及从其他数据处理器接收来自系统控制器的对应于存储器事务请求的高速缓存访​​问请求。 在优选实施例中，每个存储器事务请求被分类为两个不同的主类之一：包括读存储器访问请求的第一事务类和包括回写存储器访问请求的第二事务类。 主接口和系统控制器具有对应的并行请求队列，每个主类一个，用于发送和接收存储器访问请求。 系统控制器还包括用于处理每个存储器事务请求的存储器事务请求逻辑和具有一组重复高速缓存标签（Dtags）的重复高速缓存索引，包括与相关联的数据处理器中的每个主高速缓存标签相对应的一个高速缓存标签。

公开(公告)号：US5634068A

公开(公告)日：1997-05-27

申请号：US415175

申请日：1995-03-31

申请人： Satyanarayana Nishtala ,  Zahir Ebrahim ,  William C. Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

发明人： Satyanarayana Nishtala ,  Zahir Ebrahim ,  William C. Van Loo ,  Kevin Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0822

摘要： A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. All of the sub-systems include a port that transmits and receives data as data packets of a fixed size. At least two of the sub-systems are data processors, each having a respective cache memory and a respective set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. The system controller maintains a set of duplicate cache tags (Dtags) for each of the data processors. The data processors each include master cache logic for updating the master cache tags, while the system controller includes logic for updating the duplicate cache tags. Memory transaction request logic simultaneously looks up the second cache tag in each of the sets of duplicate cache tags corresponding to the memory transaction request. It then determines which one of the cache memories and main memory to couple to the requesting data processor based on the second cache states and the address tags stored in the corresponding second cache tags. Duplicate cache update logic simultaneously updates all of the corresponding second cache tags in accordance with predefined cache tag update criteria.

摘要翻译： 多处理器计算机系统具有多个子系统和耦合到系统控制器的主存储器。 互连模块根据从系统控制器接收的互连控制信号，互连主存储器和子系统。 所有子系统都包括一个端口，该端口作为固定大小的数据包发送和接收数据。 至少两个子系统是数据处理器，每个数据处理器具有相应的高速缓冲存储器和相应的主缓存标签集（Etags），包括由高速缓存存储器存储的每个数据块的一个高速缓存标签。 系统控制器为每个数据处理器维护一组重复的缓存标签（Dtags）。 数据处理器各自包括用于更新主缓存标签的主缓存逻辑，而系统控制器包括用于更新重复高速缓存标签的逻辑。 存储器事务请求逻辑同时查找对应于存储器事务请求的每组重复高速缓存标签中的第二高速缓存标签。 然后，基于存储在相应的第二高速缓存标签中的第二高速缓存状态和地址标签，确定哪个高速缓冲存储器和主存储器耦合到请求数据处理器。 重复的高速缓存更新逻辑根据预定义的缓存标签更新标准同时更新所有相应的第二高速缓存标签。

公开(公告)号：US5907485A

公开(公告)日：1999-05-25

申请号：US414875

申请日：1995-03-31

申请人： William C. Van Loo ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  Kevin B. Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

发明人： William C. Van Loo ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  Kevin B. Normoyle ,  Leslie Kohn ,  Louis F. Coffin, III

IPC分类号： G06F9/46 ,  G06F13/24 ,  G05B15/00

CPC分类号： G06F9/546 ,  G06F13/24

摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.

摘要翻译： 本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。 计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。 主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。 主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。 来自下游队列的确认向发送方指示在其中存在另一个事务的空间。 因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

公开(公告)号：US5692197A

公开(公告)日：1997-11-25

申请号：US414879

申请日：1995-03-31

申请人： Charles E. Narad ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Kevin B. Normoyle ,  Louis F. Coffin, III ,  Leslie Kohn

发明人： Charles E. Narad ,  Zahir Ebrahim ,  Satyanarayana Nishtala ,  William C. Van Loo ,  Kevin B. Normoyle ,  Louis F. Coffin, III ,  Leslie Kohn

IPC分类号： G06F1/32 ,  G06F15/16 ,  G06F15/177

CPC分类号： G06F1/3209

摘要： A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.

摘要翻译： 一种用于主动管理计算机网络的整体功耗的方法和装置，其包括彼此互连的多个计算机系统。 反过来，每个计算机系统具有一个或多个模块。 计算机网络的每个计算机系统能够独立地启动向省电模式转变，即“休眠”状态，同时保持其网络接口“活着”并且完全可操作。 随后，当由确定性或异步事件触发时，每个计算机系统可以独立地转换回完全操作状态，即“清醒”状态。 因此，计算机系统的睡眠状态对于计算机网络是透明的。 确定性事件是由计算机系统在内部触发的事件，例如内部定时器在午夜唤醒计算机系统以执行诸如日常磁带备份的家务杂务。 相反，异步事件的来源本质上是外部的，包括输入/​​输出（I / O）活动。 整个网络的错觉始终是完全可操作的，因为每个计算机系统的系统控制器，互连和网络接口在选定的模块和外围设备关闭电源时保持完全可操作。 因此，每个计算机系统能够通过断电所选择的模块来迅速地从睡眠状态唤醒，从而实现功率节省，而不需要静态关闭计算机网络，即没有计算机的整体性能和响应 网络。

公开(公告)号：US20060125937A1

公开(公告)日：2006-06-15

申请号：US11010032

申请日：2004-12-10

申请人： Didier LeGall ,  Leslie Kohn ,  Elliot Linzer

发明人： Didier LeGall ,  Leslie Kohn ,  Elliot Linzer

IPC分类号： H04N5/262

CPC分类号： H04N5/23296 ,  H04N5/232

摘要： A camera system and a method for zooming the camera system is disclosed. The method generally includes the steps of (A) generating an electronic image by sensing an optical image received by the camera, the sensing including electronic cropping to a window size to establish an initial resolution for the electronic image, (B) generating a final image by decimating the electronic image by a decimation factor to a final resolution smaller than the initial resolution and (C) changing a zoom factor for the final image by adjusting both of the decimation factor and the window size.

摘要翻译： 公开了一种相机系统和用于缩放相机系统的方法。 该方法通常包括以下步骤：（A）通过感测由相机接收的光学图像来生成电子图像，所述感测包括电子裁剪至窗口大小以建立电子图像的初始分辨率，（B）生成最终图像 通过抽取因子将电子图像抽取到小于初始分辨率的最终分辨率，以及（C）通过调节抽取因子和窗口大小来改变最终图像的缩放因子。

公开(公告)号：US20070162911A1

公开(公告)日：2007-07-12

申请号：US11686317

申请日：2007-03-14

申请人： Leslie Kohn ,  Kunle Olukotun ,  Michael Wong

发明人： Leslie Kohn ,  Kunle Olukotun ,  Michael Wong

IPC分类号： G06F9/46

CPC分类号： H04L47/10 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/1423 ,  G06F9/30007 ,  G06F9/30043 ,  G06F9/3851 ,  G06F9/3879 ,  G06F9/3891 ,  G06F11/108 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F13/1689 ,  G06F21/72 ,  G09G2352/00 ,  G09G2360/121 ,  G09G2370/022 ,  G09G2370/20 ,  G11C11/4074 ,  H04L29/06 ,  H04L45/745 ,  H04L47/2441 ,  H04L49/90 ,  H04L49/9057 ,  H04L49/9089 ,  H04L69/22 ,  Y02D10/13 ,  Y02D10/14

摘要： In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.

摘要翻译： 在一个实施例中，提供处理器。 处理器包括至少两个核，其中每个核包括第一级高速缓冲存储器。 每个核心都是多线程的。 在另一个实施例中，每个芯包括四个螺纹。 在另一个实施例中，包括交叉开关。 提供了通过横杆与内核通信的多个缓存组存储器。 多个高速缓存组存储器中的每一个与主存储器接口通信。 在另一个实施例中，还包括与多个高速缓存组存储器中的每一个通信的缓冲器开关核心。 还提供了用于优化多线程处理器核的利用率的服务器和方法。

公开(公告)号：US5842225A

公开(公告)日：1998-11-24

申请号：US395579

申请日：1995-02-27

申请人： Leslie Kohn

发明人： Leslie Kohn

IPC分类号： G06F9/38 ,  G06F9/312 ,  G06F9/32 ,  G06F12/10 ,  G06F12/14

CPC分类号： G06F9/30043 ,  G06F12/1027 ,  G06F12/145 ,  G06F12/1458 ,  G06F2212/684

摘要： A non-fault-only (NFO) bit is included in the translation table entry for each page. If the NFO bit is set, non-faulting loads accessing the page will cause translations to occur. Any other access to the non-fault-only page is an error, and will cause the processor to fault. A non-faulting load behaves like a normal load except that it never produces a fault even when applied to a page with the NFO bit set. The NFO bit in a translation table entry marks a page that is mapped for safe access by non-faulting loads, but can still cause a fault by other, normal accesses. The NFO bit indicates which pages are illegal. Selected pages, such as the virtual page 0x0, can be mapped in the translation table. Whenever a null-pointer is dereferenced by a non-faulting load, a translation lookaside buffer (TLB) hit will occur, and zero will be returned immediately without trapping to software to find the requested page. A second embodiment provides that when the operating system software routine invoked by a TLB miss discovers that a non-faulting load has attempted to access an illegal virtual page that was not previously translated in the translation table, the operating system creates a translation table entry for that virtual page mapping it to a physical page of all zeros and asserting the NFO bit for that virtual page.

摘要翻译： 每个页面的转换表项中都包含非故障（NFO）位。 如果NFO位被设置，访问页面的无故障加载将导致转换。 对非故障页面的任何其他访问都是错误，并将导致处理器出现故障。 非故障负载的作用就像正常负载，除了即使应用于设置了NFO位的页面，它也不会产生故障。 翻译表条目中的NFO位标记了一个被非故障负载安全访问映射的页面，但仍然可能由其他正常访问引起故障。 NFO位指示哪些页面是非法的。 所选页面，如虚拟页面0x0，可以映射到转换表中。 无论何时一个空指针由非故障负载解除引用，将会发生转换后备缓冲区（TLB）命中，零将立即返回，而不会陷入软件以查找请求的页面。 第二实施例规定，当由TLB错误调用的操作系统软件例程发现非故障负载尝试访问以前未在转换表中翻译的非法虚拟页面时，操作系统创建用于 该虚拟页面将其映射到全零的物理页面并断言该虚拟页面的NFO位。

公开(公告)号：US5802575A

公开(公告)日：1998-09-01

申请号：US946611

申请日：1997-10-07

申请人： Dale Greenley ,  Leslie Kohn ,  Ming Yeh ,  Greg Williams

发明人： Dale Greenley ,  Leslie Kohn ,  Ming Yeh ,  Greg Williams

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/30043 ,  G06F12/0853 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3875 ,  G06F12/0859

摘要： A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array.

摘要翻译： 缓存的双端口标签阵列允许通过在新的LOAD指令正在访问标签阵列以检查缓存命中的相同周期期间返回的旧LOAD指令的未命中数据来同时访问标签数组。 因为加载缓冲区排队LOAD指令，所以当新的LOAD指令正在访问标记数组以检查缓存命中时，错过高速缓存的较旧LOAD指令的缓存标签将返回。 用于计算和维护加载缓冲器中的命中位的方法和装置执行新分派的LOAD在其已经排队到加载缓冲器中并等待所有较旧的LOAD被处理之后是否将击中高速缓存的确定。 加载缓冲区数据条目包括命中位和处理LOAD指令所需的所有信息，并计算必须缓冲的未来LOAD指令的命中位。 一种用于服务LOAD指令的方法和装置，其中高速缓存的数据阵列部分和标签阵列部分的访问被解耦，允许在加载缓冲器中的LOAD被延迟之后数据阵列的延迟访问，而不重新加载 标签数组。