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    Stomach-proected Alpha-amylase to Improve the Utilization of Diet Energy and Growth Performance of Animals
    1.
    发明申请
    Stomach-proected Alpha-amylase to Improve the Utilization of Diet Energy and Growth Performance of Animals 审中-公开
    胃调查的α-淀粉酶，以提高饮食能量的利用和动物的生长性能

    公开(公告)号：US20110183032A1

    公开(公告)日：2011-07-28

    申请号：US13007866

    申请日：2011-01-17

    申请人： Zhiyong Duan ,  Yongcai Liu ,  Ye Lao ,  Dong Chen ,  Jun Ma

    发明人： Zhiyong Duan ,  Yongcai Liu ,  Ye Lao ,  Dong Chen ,  Jun Ma

    IPC分类号： A23K1/165

    CPC分类号： A23K50/60 ,  A23K20/189 ,  A23K40/30 ,  A23K50/30 ,  A23K50/75

    摘要： A protected α-amylase is described. Pelletization and encapsulation technology, in which slow-release materials and pH-sensitive materials are used to protect the α-amylase from inactivation at low pH. The protected α-amylase was found to be highly stable after as long as 3-hour treatment in acid (pH 3.0). When treated in pH 3.0 for 1 hour and followed by treatment with lipase and pancreatin in pH 7.0 for 2 hour to simulate in vivo environment, it was found that α-amylase was fully released and measurable. In addition, the protected α-amylase showed superior efficacy to the unprotected α-amylase. The protected α-amylase also demonstrated enhanced thermostability.

    摘要翻译： 描述了保护的α-淀粉酶。 造粒和包封技术，其中使用缓释材料和pH敏感材料来保护α-淀粉酶在低pH下失活。 发现保护的α-淀粉酶在酸（pH3.0）中长达3小时处理后是高度稳定的。 当在pH3.0中处理1小时，然后用pH7.0的脂肪酶和胰酶处理2小时以模拟体内环境时，发现α-淀粉酶被完全释放并可测量。 此外，受保护的α-淀粉酶对未保护的α-淀粉酶表现出优异的功效。 受保护的α-淀粉酶也表现出增强的热稳定性。

    Array substrate and liquid crystal display
    7.
    发明授权
    Array substrate and liquid crystal display 有权
    阵列基板和液晶显示

    公开(公告)号：US09250477B2

    公开(公告)日：2016-02-02

    申请号：US13524144

    申请日：2012-06-15

    申请人： Dong Chen ,  Xue Dong ,  Cheng Li

    发明人： Dong Chen ,  Xue Dong ,  Cheng Li

    IPC分类号： G02F1/1337 ,  G02F1/1343

    CPC分类号： G02F1/133707 ,  G02F1/134309 ,  G02F2001/134381

    摘要： An embodiment of the present disclosure provides an array substrate, and the array substrate including: at least a data line and at least a gate line; and a plurality of pixel units defined by the data line and the gate line. Each of the plurality of pixel units includes a thin film transistor, a first electrode and a second electrode, and the first electrode and the second electrode overlap each other and are insulated from each other and the second electrode is positioned above the first electrode. An alignment film is formed on a surface of the array substrate, a direction of the second electrode and one side of the array substrate form a predetermined angle and a rubbing direction of the alignment film is parallel to the one side of the array substrate.

    摘要翻译： 本公开的实施例提供阵列基板，并且阵列基板包括：至少数据线和至少栅极线; 以及由数据线和栅极线限定的多个像素单元。 多个像素单元中的每一个包括薄膜晶体管，第一电极和第二电极，并且第一电极和第二电极彼此重叠并且彼此绝缘，并且第二电极位于第一电极的上方。 在阵列基板的表面上形成取向膜，第二电极的方向和阵列基板的一侧形成预定的角度，并且取向膜的摩擦方向平行于阵列基板的一侧。

    T-Star interconnection network topology
    8.
    发明授权
    T-Star interconnection network topology 有权
    T星互连网络拓扑

    公开(公告)号：US09137098B2

    公开(公告)日：2015-09-15

    申请号：US13584300

    申请日：2012-08-13

    申请人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    发明人： Dong Chen ,  Paul W. Coteus ,  Noel A. Eisley ,  Philip Heidelberger ,  Robert M. Senger ,  Yutaka Sugawara

    IPC分类号： H04L12/715 ,  H04L12/24

    CPC分类号： H04L41/0663 ,  H04L41/12 ,  H04L41/145 ,  H04L45/04

    摘要： According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.

    摘要翻译： 根据本发明的一个实施例，提供了一种为节点组网格构建网络通信的方法，所述网格包括M维网格，每个节点组包括N个节点，其中M大于或等于1，并且N 大于1，其中每个节点包括路由器。 该方法包括通过组内链路将每个节点组中的每个节点直接连接到节点组中的每个其他节点，并将M维网格的每个节点组中的每个节点直接连接到M维中的每个相邻节点组中的节点 网格通过组间链接。

    Predicting LED parameters from electroluminescent semiconductor wafer testing
    9.
    发明授权
    Predicting LED parameters from electroluminescent semiconductor wafer testing 有权
    从电致发光半导体晶圆测试预测LED参数

    公开(公告)号：US09069035B2

    公开(公告)日：2015-06-30

    申请号：US13333433

    申请日：2011-12-21

    申请人： Dong Chen

    发明人： Dong Chen

    IPC分类号： G06F19/00 ,  G01R27/00 ,  G01R31/26 ,  H05B31/00 ,  F21V8/00 ,  F21Y103/00 ,  G01R31/265

    CPC分类号： G01R31/2648 ,  F21V29/83 ,  F21V2200/00 ,  F21Y2103/00 ,  G01R31/2656 ,  H05B31/00 ,  H05B2206/00

    摘要： A diode model and conductive-probe measurements taken at the wafer lever are used to predict the characterization parameters of a semiconductor device manufactured from the wafer. A current-voltage curve (I-V) model that expresses a current-voltage relationship as a function of resistance, ideality factor, and reverse saturation current is fitted to a number of conductive-probe measurement data. The current-voltage curve (I-Vd) for the device is then estimated by subtracting from the (I-V) model the product of current times the resistance produced by fitting the (I-V) model.

    摘要翻译： 使用在晶圆杠杆处获取的二极管模型和导电探针测量来预测从晶片制造的半导体器件的表征参数。 表示作为电阻，理想因子和反向饱和电流的函数的电流 - 电压关系的电流 - 电压曲线（I-V）模型拟合到多个导电探针测量数据。 然后通过从（I-V）模型中减去当前乘积乘以（I-V）模型产生的电阻的乘积，来估计器件的电流 - 电压曲线（I-Vd）。