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公开(公告)号：US06610999B2
公开(公告)日：2003-08-26
申请号：US09851692
申请日：2001-05-08
IPC分类号： H01L310256
CPC分类号： H01L29/1608 , H01L27/0814 , H01L27/095 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/872
摘要： A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.
摘要翻译： 肖特基整流器具有多个阶段，具有基本相同或非常相似的结构。 每个级包括氮化物基半导体层，形成在半导体层的一个表面上的肖特基接触和形成在半导体层的相对表面上的欧姆接触。 肖特基层由具有高金属功能的金属材料形成，并且欧姆接触由具有低金属功函数的金属材料形成。 至少一个阶段是位于两个相邻阶段之间的中间阶段，使得中间阶段的肖特基接触和相邻阶段之一的欧姆接触被连接在一起，并且使得中间阶段的欧姆接触和 另一个相邻级的肖特基接触被连接在一起。
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公开(公告)号：US06229193B1
公开(公告)日：2001-05-08
申请号：US09283653
申请日：1999-04-01
IPC分类号： H01L27095
CPC分类号： H01L29/1608 , H01L27/0814 , H01L27/095 , H01L29/2003 , H01L29/47 , H01L29/475 , H01L29/872
摘要： A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.
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公开(公告)号：US6093952A
公开(公告)日：2000-07-25
申请号：US283009
申请日：1999-03-31
IPC分类号： H01L21/318 , H01L29/872 , H01L27/095
CPC分类号： H01L21/318 , H01L29/872
摘要： A Schottky high power rectifier having a nitride insulator formed on the surface of a GaN substrate. The nitride insulator increases the electric field breakdown suppression at or near the surface of the rectifier below the insulator. In a preferred embodiment, the nitride insulator is an epitaxially grown aluminum nitride insulator.
摘要翻译： 肖特基大功率整流器具有形成在GaN衬底的表面上的氮化物绝缘体。 氮化物绝缘体增加了绝缘体下面整流表面处或附近的电场击穿抑制。 在优选实施例中，氮化物绝缘体是外延生长的氮化铝绝缘体。
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4.发明授权High power devices based on gallium nitride and aluminum gallium nitride semiconductor heterostructures 失效基于氮化镓和氮化镓铝半导体异质结构的大功率器件
公开(公告)号：US6144045A
公开(公告)日：2000-11-07
申请号：US285484
申请日：1999-04-02
IPC分类号： H01L29/201 , H01L29/205 , H01L29/74 , H01L29/87
CPC分类号： H01L29/87 , H01L29/201 , H01L29/205 , H01L29/74
摘要： High power thyristor-type devices comprising a first layer of p-type doped semiconductor alloy aluminum gallium nitride, a second layer of n-type doped aluminum gallium nitride with lower aluminum content than the first layer, a third layer of p-type doped aluminum gallium nitride with a higher aluminum content than the second layer, and a fourth layer of aluminum gallium nitride of n-type doping. The difference in hole and electron energies (band offsets) across the interface between aluminum gallium nitride and gallium nitride are such that hole and electron transfer are enhanced from aluminum gallium nitride to gallium nitride, or hole and electron transfer are suppressed from gallium nitride to aluminum gallium nitride. Aluminum content in layers 1 and 2 is chosen such that hole transfer in the forward biased conduction state of the device is enhanced, and suppressed in the reverse biased blocking state of the device. Aluminum content in layers 2 and 3 is chosen such that hole transfer in the forward biased blocking state of the device is suppressed, which reduces leakage current and enhances hole transfer into layer 2 when the device is changing from the forward biased blocking state to the forward biased conduction state. Triggering of the device may be provided by a gate contact to the third layer. Various exemplary embodiments are disclosed.
摘要翻译： 大功率晶闸管型器件包括第一层p型掺杂半导体合金氮化铝镓，具有比第一层低的铝含量的n型掺杂的氮化铝镓的第二层，第三层p型掺杂的铝 具有比第二层高的铝含量的氮化镓，以及n型掺杂的第四层氮化镓铝。 氮化镓和氮化镓之间的界面上的空穴和电子能量（带偏移）的差异使得从氮化镓铝到氮化镓的空穴和电子转移增强，或者从氮化镓到铝的空穴和电子转移被抑制 氮化镓。 选择层1和2中的铝含量使得器件的正向偏置导通状态中的空穴传输增强，并且在器件的反向偏置阻塞状态下被抑制。 选择层2和3中的铝含量，使得器件的正向偏压阻挡状态下的空穴传输受到抑制，这降低了泄漏电流并且当器件从正向偏置阻塞状态向前转变时增强了到层2中的空穴传输 偏置导通状态。 可以通过与第三层的栅极接触来提供器件的触发。 公开了各种示例性实施例。
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公开(公告)号：US06078055A
公开(公告)日：2000-06-20
申请号：US44082
申请日：1998-03-18
申请人： Paul M. Bridger , Thomas C. McGill
发明人： Paul M. Bridger , Thomas C. McGill
IPC分类号： B82B3/00 , G03F7/20 , H01J37/30 , H01J37/304
CPC分类号： G03F7/70383 , B82Y10/00 , B82Y40/00 , H01J37/3174 , G01Q80/00 , H01J2237/31776 , Y10S977/859 , Y10S977/868
摘要： A proximity lithography device using a modified electric field. In the preferred embodiment, the modified electric field is formed by illuminating a tip of a scanning probe in close proximity of the resist surface with a laser. In an alternate embodiment, the modified electric field is formed by positioning a tip of a scanning probe within close proximity of the resist surface, where illumination from a laser is in total internal reflection within the resist. The proximity of the tip to the resist surface creates a tunneling effect and forms the modified electric field. The modified electric field alters the resist for lithographic patterning.
摘要翻译： 使用改性电场的接近光刻装置。 在优选实施例中，通过用激光照射紧邻抗蚀剂表面的扫描探针的尖端来形成修改的电场。 在替代实施例中，通过将扫描探针的尖端定位在抗蚀剂表面的紧密附近来形成修改的电场，其中来自激光器的照射在抗蚀剂内完全内反射。 尖端与抗蚀剂表面的接近产生隧道效应并形成修改的电场。 改性电场改变光刻胶用于光刻图案化。
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6.发明授权Method for fabricating transistorless, multistable current-mode memory cells and memory arrays 失效用于制造无晶体管，多电流电流模式存储器单元和存储器阵列的方法
公开(公告)号：US6015738A
公开(公告)日：2000-01-18
申请号：US972118
申请日：1997-11-17
申请人： Harold J. Levy , Thomas C. McGill
发明人： Harold J. Levy , Thomas C. McGill
IPC分类号： G11C11/39 , G11C11/56 , H01L27/102 , H01L21/8246
CPC分类号： H01L27/1021 , G11C11/39 , G11C11/56 , G11C2211/5614 , Y10S438/979
摘要： A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind.
摘要翻译： 用于将信息存储为两个可能的双稳电流状态之一的无晶体管存储单元包括：（i）至少一个具有N型负差分电阻的第一无晶体管器件，包括高阻抗区域，低阻抗区域和负电阻 区域并具有极性，以及（ii）呈现指数或线性电流 - 电压特性并耦合到第一无晶体管器件的至少一个第二无晶体管器件。 无电晶体管存储单元的读/写操作在当前模式下执行。 一种用于制造存储单元的自对准三维结构的方法包括以下步骤：（i）形成第一导电层，（ii）在第一导电层上形成第一半导体层，（iii）形成第二半导体 （iv）图案化第二半导体层，（v）蚀刻第二半导体层，第一半导体层和第一导电层，（vi）在第二半导体层上形成第二导电层（ vii）图案化和蚀刻第二导电层，以及（viii）使用第二导电层作为掩模蚀刻第二半导体层以形成第二种导电层的多个半导体器件，并且使用第二导电层作为第一导电层来蚀刻第一半导体层 掩模以形成第一类的多个半导体器件。
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7.发明授权Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same 失效无晶体管，多电流电流模式存储单元和存储器阵列以及读写方法
公开(公告)号：US5745407A
公开(公告)日：1998-04-28
申请号：US628821
申请日：1996-04-05
申请人： Harold J. Levy , Thomas C. McGill
发明人： Harold J. Levy , Thomas C. McGill
IPC分类号： G11C11/39 , G11C11/56 , H01L27/102 , G11C11/00 , G11C11/36 , H01L27/108
CPC分类号： H01L27/1021 , G11C11/39 , G11C11/56 , G11C2211/5614 , Y10S438/979
摘要： A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind, wherein the semiconducting devices of the first kind exhibit N-type negative differential resistance, and the semiconducting devices of the second kind may exhibit exponential or linear current-voltage characteristics.
摘要翻译： 用于将信息存储为两个可能的双稳电流状态之一的无晶体管存储单元包括：（i）至少一个具有N型负差分电阻的第一无晶体管器件，包括高阻抗区域，低阻抗区域和负电阻 区域并具有极性，以及（ii）呈现指数或线性电流 - 电压特性并耦合到第一无晶体管器件的至少一个第二无晶体管器件。 无电晶体管存储单元的读/写操作在当前模式下执行。 一种用于制造存储单元的自对准三维结构的方法包括以下步骤：（i）形成第一导电层，（ii）在第一导电层上形成第一半导体层，（iii）形成第二半导体 （iv）图案化第二半导体层，（v）蚀刻第二半导体层，第一半导体层和第一导电层，（vi）在第二半导体层上形成第二导电层（ vii）图案化和蚀刻第二导电层，以及（viii）使用第二导电层作为掩模蚀刻第二半导体层以形成第二种导电层的多个半导体器件，并且使用第二导电层作为第一导电层来蚀刻第一半导体层 掩模形成第一种半导体器件，其中第一类半导体器件表现出N型负微分电阻，半导体器件 第二种的导电装置可以呈现指数或线性的电流 - 电压特性。
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公开(公告)号：US5371409A
公开(公告)日：1994-12-06
申请号：US153783
申请日：1993-11-16
CPC分类号： H01L33/28 , H01L33/0029 , H01S5/327 , H01S5/0421 , H01S5/3201 , H01S5/321 , H01S5/3211 , H01S5/322
摘要： Type-II semiconductor heterojunction light emitting devices formed on a substrate are described wherein a graded injection layer is used to accelerate electrons over the electron barrier formed by the junction. Further, wide band gap semiconductor LEDs and lasers are proposed formed of II-VI materials which emit light in the blue and green wavelengths. Particularly, a system composed of n-CdSe:Al/Mg.sub.x Cd.sub.1-x Se/Mg.sub.y Zn.sub.1-y Te/p-ZnTe are described where the value of y determines the wavelength of the emitted light in the green or blue region and x varies across the graded injection layer for raising the energy levels of excited electrons.
摘要翻译： 描述了形成在衬底上的II型半导体异质结发光器件，其中使用渐变注入层来加速由结形成的电子势垒上的电子。 此外，提出了由发射蓝色和绿色波长的光的II-VI材料形成的宽带隙半导体LED和激光器。 具体说，描述了由n-CdSe：Al / MgxCd1-xSe / MgyZn1-yTe / p-ZnTe组成的系统，其中y的值决定了绿色或蓝色区域中发射的光的波长，x在分级注入 提高激发电子能级的层。
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公开(公告)号：US07189358B2
公开(公告)日：2007-03-13
申请号：US09923582
申请日：2001-08-07
IPC分类号： G01N15/06 , G01N33/00 , G01N33/48 , H01L21/302 , E03B1/00
CPC分类号： F04B43/14 , B01L3/502707 , B01L3/50273 , B01L2200/10 , B01L2300/0654 , B01L2300/087 , B01L2300/0887 , B01L2400/0481 , F04B43/043 , Y10T137/0318 , Y10T137/4673 , Y10T436/11 , Y10T436/25
摘要： An integrated micropump or a plurality of integrated micropumps are communicated to a plurality of analysis chambers. A plurality of integrated analysis chambers include integrated analysis devices to test a fluid for an analyte. The micropumps continuously or periodically pump the fluid into the analysis chambers and flush the analysis chambers after analysis of the analyte. In one embodiment, the analysis device comprises an integrated LED and an integrated optical detector. The LED and detector are tuned to an optical absorption line of the analyte. The micropumps are composed of nitrides of B, Al, Ga, In, Tl or combinations thereof and fabricated using photoelectrochemical techniques. The analysis chambers, and micropumps including the analysis devices are simultaneously fabricated during which fabrication of the micropumps and the analysis devices are masked from the photoelectrochemical techniques.
摘要翻译： 集成的微型泵或多个集成的微型泵将传递到多个分析室。 多个综合分析室包括用于测试分析物的流体的集成分析装置。 微型泵将连续或周期性地将流体泵入分析室，并在分析物分析后冲洗分析室。 在一个实施例中，分析装置包括集成LED和集成光学检测器。 LED和检测器被调谐到分析物的光吸收线。 微量泵由B，Al，Ga，In，Tl或其组合的氮化物组成，并使用光电化学技术制造。 同时制造分析室和包括分析装置的微型泵，在此期间微光泵和分析装置的制造被光电化学技术掩蔽。
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10.发明授权公开(公告)号：US06579068B2
公开(公告)日：2003-06-17
申请号：US09923483
申请日：2001-08-07
IPC分类号： F04B1924
CPC分类号： F04B43/12 , F04B43/043
摘要： A suspended p-GaN membrane is formed using photochemical etching which membrane can then be used in a variety of MEMS devices. In the illustrated embodiment a pump is comprised of the p-GaN membrane suspended between two opposing, parallel n-GaN support pillars, which are anchored to a rigid substrate below the pillars. The p-GaN membrane bows upward between the pillars in order to relieve stress built up during the epitaxial growth of membrane. This bowing substantially increases the volume of the enclosed micro-channel defined between membrane and substrate below. The ends of membrane are finished off by a gradual transition to the flat underlying n-GaN layer in which fluidic channels may also be defined to provide inlet and outlet channels to microchannel. A traveling wave or sequential voltage applied to the electrodes causes the membrane to deform and provide a peristaltic pumping action in the microchannel.
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