Multiphase clock generator and associated frequency synthesizer

    公开(公告)号:US11012082B1

    公开(公告)日:2021-05-18

    申请号:US16924241

    申请日:2020-07-09

    发明人: Che-Wei Chang

    摘要: A multiphase clock generator includes a current mirror, a voltage controller, a pseudo-resistor circuit and a first delaying circuit. The current mirror includes a receiving terminal, a first mirroring terminal and a second mirroring terminal. The voltage controller is connected with the receiving terminal of the current mirror. A feedback terminal of the voltage controller is connected with the first mirroring terminal of the current mirror. A first terminal of the pseudo-resistor circuit is connected with the first mirroring terminal of the current mirror. A second terminal of the pseudo-resistor circuit is connected with a ground terminal. The first delaying circuit is connected with the second terminal of the pseudo-resistor circuit. An input terminal of the first delaying circuit receives a first input clock signal. An output terminal of the first delaying circuit generates a first delayed clock signal.

    FLASH MEMORY AND ASSOCIATED PROGRAMMING METHOD
    2.
    发明申请
    FLASH MEMORY AND ASSOCIATED PROGRAMMING METHOD 有权
    闪存和相关编程方法

    公开(公告)号:US20140211562A1

    公开(公告)日:2014-07-31

    申请号:US13755045

    申请日:2013-01-31

    IPC分类号: G11C16/10

    摘要: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

    摘要翻译: 闪速存储器包括编程电压发生器,多个存储器单元,限流器和多位程序控制单元。 程序电压发生器用于在检测周期期间提供恒定的编程电压,并在编程周期期间提供动态可调节的编程电压。 多个存储单元将多个漏极电流和多个数据线电压输出到多条数据线。 电流限制器用于接收参考电流和参考电压,从而控制多个漏极电流。 在检测周期期间,由多位程序控制单元检测具有最小电压电平的多条数据线电压的指定数据线电压。 在编程周期中,指定的数据线电压用作反馈电压,动态可调程序电压由编程电压发生器根据反馈电压产生。

    Sensing device for non-volatile memory

    公开(公告)号:US12027214B2

    公开(公告)日:2024-07-02

    申请号:US17949255

    申请日:2022-09-21

    发明人: Che-Wei Chang

    摘要: A sensing device for a non-volatile memory includes a reference circuit, two switches, a sensing circuit and a judging circuit. The reference circuit is connected to a first node. A first terminal of the first switch is connected with the first node and a control terminal of the first switch receives an inverted reset pulse. A first terminal of the second switch is connected with the first node, a second terminal of the second switch receives a ground voltage, and a control terminal of the second switch receives a reset pulse. The sensing circuit is connected between the second terminal of the first switch and a second node. The sensing circuit generates a first sensed current. The judging circuit is connected to the second node. The judging circuit receives the first sensed current and generates an output data according to the first sensed current.

    Sensing circuit and method for multi-level memory cell

    公开(公告)号:US11308996B2

    公开(公告)日:2022-04-19

    申请号:US17241112

    申请日:2021-04-27

    发明人: Che-Wei Chang

    摘要: A sensing circuit includes a cell clock generator, a reference clock generator, a counter, a latching signal generator, a latch and a count-to-state conversion circuit. The cell clock generator receives a cell current from a selected memory cell, and converts the cell current into a cell clock signal. The reference clock generator converts a reference current into a reference clock signal. The count receives the cell clock signal, and generates a count value. When a pulse number of the reference clock signal reaches a predetermined count value, the latching signal generator activates a latching signal. When the latching signal is activated, the latch issues a latched count value. The count-to-state conversion circuit receives the latched count value, and issues a state value. A storage state of the selected memory cell is determined according to the state value.

    Sense amplifier for a memory cell with a fast sensing speed
    5.
    发明授权
    Sense amplifier for a memory cell with a fast sensing speed 有权
    用于具有快速感测速度的存储单元的感测放大器

    公开(公告)号:US09305611B2

    公开(公告)日:2016-04-05

    申请号:US14736271

    申请日:2015-06-11

    发明人: Che-Wei Chang

    摘要: A sense amplifier comprises a cell current generator, a reference current generator, a first and a second charge/discharge elements, a first and a second voltage trigger circuits, and a data holder. The cell current generator is used to output a cell current of a memory cell. The reference current generator is used to output a duplicated reference current. The first and the second charge/discharge elements are used to convert the cell current and the duplicated reference current to voltage signals respectively. The first voltage trigger circuit is used to output a data signal according to a voltage signal outputted from the first charge/discharge element. The second voltage trigger circuit is used to output a hold control signal according to a voltage signal outputted from the second charge/discharge element. The data holder is used to hold a voltage level of the data signal according to the hold control signal.

    摘要翻译: 感测放大器包括电池电流发生器,参考电流发生器,第一和第二充电/放电元件,第一和第二电压触发电路以及数据保持器。 电池电流发生器用于输出存储单元的单元电流。 参考电流发生器用于输出重复的参考电流。 第一和第二充电/放电元件分别用于将电池电流和复制的参考电流转换为电压信号。 第一电压触发电路用于根据从第一充电/放电元件输出的电压信号输出数据信号。 第二电压触发电路用于根据从第二充电/放电元件输出的电压信号输出保持控制信号。 数据保持器用于根据保持控制信号保持数据信号的电压电平。

    Trimming circuit and method applied to voltage generator
    6.
    发明授权
    Trimming circuit and method applied to voltage generator 有权
    微调电路和方法应用于电压发生器

    公开(公告)号:US09270259B2

    公开(公告)日:2016-02-23

    申请号:US14280973

    申请日:2014-05-19

    发明人: Che-Wei Chang

    IPC分类号: H03K4/06 H03K5/08 H02M3/07

    CPC分类号: H03K5/08 H02M3/07

    摘要: A trimming method for a voltage generator is provided. The voltage generator generates an output voltage according to a reference voltage. The trimming method includes the following steps. Firstly, in a step (a), an initial value of a trimming code is provided. Then, in a step (b), the reference voltage is generated to the voltage generator according to the trimming code, so that the output voltage is correspondingly generated by the voltage generator. Then, in a step (c), an average voltage of the output voltage is compared with a target voltage. If the average voltage does not reach the target voltage, the trimming code is gradually changed, and the step (b) is repeatedly done. If the average voltage reaches the target voltage, the trimming code is locked.

    摘要翻译: 提供了一种用于电压发生器的修整方法。 电压发生器根据参考电压产生输出电压。 修整方法包括以下步骤。 首先,在步骤(a)中,提供修整码的初始值。 然后,在步骤(b)中,根据修整代码向电压发生器产生参考电压,使得由电压发生器相应地产生输出电压。 然后,在步骤(c)中,将输出电压的平均电压与目标电压进行比较。 如果平均电压未达到目标电压,则修整代码逐渐变化,并重复步骤(b)。 如果平均电压达到目标电压,则修整代码被锁定。

    TRIMMING CIRCUIT AND METHOD APPLIED TO VOLTAGE GENERATOR
    7.
    发明申请
    TRIMMING CIRCUIT AND METHOD APPLIED TO VOLTAGE GENERATOR 有权
    用于电压发生器的调整电路和方法

    公开(公告)号:US20150333744A1

    公开(公告)日:2015-11-19

    申请号:US14280973

    申请日:2014-05-19

    发明人: Che-Wei Chang

    IPC分类号: H03K5/08 H02M3/07

    CPC分类号: H03K5/08 H02M3/07

    摘要: A trimming method for a voltage generator is provided. The voltage generator generates an output voltage according to a reference voltage. The trimming method includes the following steps. Firstly, in a step (a), an initial value of a trimming code is provided. Then, in a step (b), the reference voltage is generated to the voltage generator according to the trimming code, so that the output voltage is correspondingly generated by the voltage generator. Then, in a step (c), an average voltage of the output voltage is compared with a target voltage. If the average voltage does not reach the target voltage, the trimming code is gradually changed, and the step (b) is repeatedly done. If the average voltage reaches the target voltage, the trimming code is locked.

    摘要翻译: 提供了一种用于电压发生器的修整方法。 电压发生器根据参考电压产生输出电压。 修整方法包括以下步骤。 首先,在步骤(a)中,提供修整码的初始值。 然后,在步骤(b)中,根据修整代码向电压发生器产生参考电压,使得由电压发生器相应地产生输出电压。 然后,在步骤(c)中,将输出电压的平均电压与目标电压进行比较。 如果平均电压未达到目标电压,则修整代码逐渐变化,并重复步骤(b)。 如果平均电压达到目标电压,则修整代码被锁定。

    SENSE AMPLIFIER FOR A MEMORY CELL WITH A FAST SENSING SPEED
    8.
    发明申请
    SENSE AMPLIFIER FOR A MEMORY CELL WITH A FAST SENSING SPEED 有权
    用于具有快速感测速度的记忆体的感测放大器

    公开(公告)号:US20160005486A1

    公开(公告)日:2016-01-07

    申请号:US14736271

    申请日:2015-06-11

    发明人: Che-Wei Chang

    IPC分类号: G11C16/28

    摘要: A sense amplifier comprises a cell current generator, a reference current generator, a first and a second charge/discharge elements, a first and a second voltage trigger circuits, and a data holder. The cell current generator is used to output a cell current of a memory cell. The reference current generator is used to output a duplicated reference current. The first and the second charge/discharge elements are used to convert the cell current and the duplicated reference current to voltage signals respectively. The first voltage trigger circuit is used to output a data signal according to a voltage signal outputted from the first charge/discharge element. The second voltage trigger circuit is used to output a hold control signal according to a voltage signal outputted from the second charge/discharge element. The data holder is used to hold a voltage level of the data signal according to the hold control signal.

    摘要翻译: 感测放大器包括电池电流发生器,参考电流发生器,第一和第二充电/放电元件,第一和第二电压触发电路以及数据保持器。 电池电流发生器用于输出存储单元的单元电流。 参考电流发生器用于输出重复的参考电流。 第一和第二充电/放电元件分别用于将电池电流和复制的参考电流转换为电压信号。 第一电压触发电路用于根据从第一充电/放电元件输出的电压信号输出数据信号。 第二电压触发电路用于根据从第二充电/放电元件输出的电压信号输出保持控制信号。 数据保持器用于根据保持控制信号保持数据信号的电压电平。

    Flash memory and associated programming method
    9.
    发明授权
    Flash memory and associated programming method 有权
    闪存和相关编程方法

    公开(公告)号:US08885405B2

    公开(公告)日:2014-11-11

    申请号:US13755045

    申请日:2013-01-31

    IPC分类号: G11C16/04 G11C16/10

    摘要: A flash memory includes a program voltage generator, plural memory units, a current limiter, and a multi-bit program control unit. The program voltage generator is used for providing a constant program voltage during a detecting cycle and providing a dynamically-adjustable program voltage during a program cycle. The plural memory units output plural drain currents and plural data line voltages to plural data lines. The current limiter is used for receiving a reference current and a reference voltage, thereby controlling the plural drain currents. During the detecting cycle, a specified data line voltage of the plural data line voltages with the minimum voltage level is detected by the multi-bit program control unit. During the program cycle, the specified data line voltage is used as a feedback voltage, and the dynamically-adjustable program voltage is generated by the program voltage generator according to the feedback voltage.

    摘要翻译: 闪速存储器包括编程电压发生器,多个存储器单元,限流器和多位程序控制单元。 程序电压发生器用于在检测周期期间提供恒定的编程电压,并在编程周期期间提供动态可调节的编程电压。 多个存储单元将多个漏极电流和多个数据线电压输出到多条数据线。 电流限制器用于接收参考电流和参考电压,从而控制多个漏极电流。 在检测周期期间,由多位程序控制单元检测具有最小电压电平的多条数据线电压的指定数据线电压。 在编程周期中,指定的数据线电压用作反馈电压,动态可调程序电压由编程电压发生器根据反馈电压产生。