公开(公告)号：US20240036263A1

公开(公告)日：2024-02-01

申请号：US17876867

申请日：2022-07-29

Applicant: Broadcom International Pte. Ltd.

Inventor： Nourhan Eid ,  Shiyun Lin ,  Naser Dalvand ,  Vivek Raghunathan

IPC: G02B6/30

CPC classification number: G02B6/305

Abstract: An optical coupler configured to couple light along a propagation direction is disclosed. The optical coupler includes a lower area. The lower area includes a waveguide including a first end, a second end, and an inversely tapered portion. The optical coupler includes an intermediary area arranged over, in a vertical direction, the lower area. The intermediary area includes two or more intermediary elements. The optical coupler includes an upper area arranged over the intermediary area. The upper area includes one or more upper elements.

公开(公告)号：US20030194139A1

公开(公告)日：2003-10-16

申请号：US10431611

申请日：2003-05-08

Applicant: Element 14 Limited ,  Broadcom UK Ltd ,  Broadcom Corporation

Inventor： Mark Taunton

IPC: G06K009/36

CPC classification number: H04N21/44016 ,  G06T9/007 ,  H04N21/23424 ,  H04N21/4384

Abstract: An image data decoding system (2) is described in which a stream of compressed image data (1) corresponding to a plurality of image channels (ChA, ChB, ChC) each comprising intra-coded pictures (I) and inter-coded pictures (B, P) is received. A selected channel within the plurality of channels is fully decoded to produce display driving data. At least one non-selected channel is at least partially processed by the system even though it is not being displayed such that if a switch is made to that non-selected channel then display driving data for that newly selected channel can be produced without having to wait for the next intra-coded picture (I) to be received. The partial processing may take the form of merely buffering the compressed data for the non-selected channel. Alternatively, reference pictures or all pictures for the non-selected channel may be either fully decoded, or partially decoded to produce spatially sub-sampled versions of the pictures of the non-selected channels.

Abstract translation: 描述图像数据解码系统（ 2 ），其中与多个图像通道（ChA，ChB，ChC）对应的压缩图像数据流（ 1 ）各自 包括帧内编码图像（I）和帧间编码图像（B，P）。 多个通道内的所选通道被完全解码以产生显示驱动数据。 至少一个未选择的信道至​​少部分地由系统处理，即使它不被显示，使得如果切换到该未选择的信道，则可以产生用于该新选择的信道的显示驱动数据，而不必 等待接收下一个帧内编码图像（I）。 部分处理可以采取仅缓冲非选择信道的压缩数据的形式。 或者，用于非选择的频道的参考图片或所有图片可以被完全解码或部分解码，以产生非选择的频道的图片的空间子采样版本。

公开(公告)号：US12216313B2

公开(公告)日：2025-02-04

申请号：US17732002

申请日：2022-04-28

Applicant: Broadcom International Pte. Ltd.

Inventor： Rebecca Schaevitz ,  Near Margalit ,  Vivek Raghunathan ,  Dicky Lee ,  Hari Potluri

IPC: G02B6/42 ,  G02B6/32

Abstract: A coupled optic system configured for collimation of light. The coupled optic system includes an optic system. The optic system includes a shelf. The shelf includes one or more optic alignment surfaces. The optic system includes one or more interface lenses coupled to the shelf. The coupled optic system includes an optical connector. The optical connector includes one or more connector lenses. The optical connector includes one or more connector alignment surfaces.

公开(公告)号：US20240030209A1

公开(公告)日：2024-01-25

申请号：US17872371

申请日：2022-07-25

Applicant: Broadcom International Pte. Ltd.

Inventor： Thomas Dungan

IPC: H01L25/18 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/5385 ,  H01L24/08 ,  H01L24/05 ,  H01L23/49816 ,  H01L2224/08225 ,  H01L2224/05647

Abstract: An interposer, and integrated circuit including an interposer, has a lower surface adapted for bump mounting and an upper surface adapted for copper bonding. An interposer layer includes active interposers and passive interposers. Bridges connect interposers in the interposer layer to produce a functionally large interposer from smaller interposer dies. A core may overlap more than one interposer in the interposer layer. Active interposers are disposed around the edge of the core with passive interposers beneath the core to facilitate heat dissipation.

公开(公告)号：US20230254109A1

公开(公告)日：2023-08-10

申请号：US17728470

申请日：2022-04-25

Applicant: Broadcom International Pte. Ltd.

Inventor： Jeffrey Grundvig

IPC: H04L7/06

CPC classification number: H04L7/06

Abstract: Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.

公开(公告)号：USRE48845E1

公开(公告)日：2021-12-07

申请号：US16103107

申请日：2018-08-14

Applicant: Broadcom Corporation

Inventor： Alexander G. MacInnis ,  Jose' R. Alvarez ,  Sheng Zhong ,  Xiaodong Xie ,  Vivian Hsiun

IPC: G06F9/38 ,  H04N19/12 ,  H04N19/122 ,  H04N19/129 ,  H04N19/157 ,  H04N19/176 ,  H04N19/423 ,  H04N19/44 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/70 ,  H04N19/82 ,  H04N19/90 ,  H04N19/91

Abstract: System and method for decoding digital video data. The decoding system employs hardware accelerators that assist a core processor in performing selected decoding tasks. The hardware accelerators are configurable to support a plurality of existing and future encoding/decoding formats. The accelerators are configurable to support substantially any existing or future encoding/decoding formats that fall into the general class of DCT-based, entropy decoded, block-motion-compensated compression algorithms. The hardware accelerators illustratively comprise a programmable entropy decoder, an inverse quantization module, a inverse discrete cosine transform module, a pixel filter, a motion compensation module and a de-blocking filter. The hardware accelerators function in a decoding pipeline wherein at any given stage in the pipeline, while a given function is being performed on a given macroblock, the next macroblock in the data stream is being worked on by the previous function in the pipeline.

公开(公告)号：US10990307B2

公开(公告)日：2021-04-27

申请号：US16047062

申请日：2018-07-27

Applicant: BROADCOM INTERNATIONAL PTE. LTD.

Inventor： Shaohua Yang ,  John Jansen

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

Abstract: A semiconductor device, memory system, and method are provided. One example of the semiconductor device is disclosed to include a host interface that enables bi-directional communications with a host computer, a processor subsystem that enables processing of read or write requests received at the host interface, and one or more storage media interfaces, each of the one or more storage media interfaces being convertible between a first configuration and a second configuration, where the first configuration of a storage media interface enables a direct connection with a computer memory device, and where the second configuration of the storage media interface enables a connection with a plurality of computer memory devices via an expander and/or re-timer.

公开(公告)号：US10901161B2

公开(公告)日：2021-01-26

申请号：US16131842

申请日：2018-09-14

Applicant: Toyota Motor Engineering & Manufacturing North America, Inc. ,  University of Ottawa ,  Broadcom Inc.

Inventor： Ercan M. Dede ,  Christopher Valdivia ,  Matthew Wilkins ,  Karin Hinzer ,  Philippe-Olivier Provost ,  Denis Masson ,  Simon Fafard

IPC: G02B6/42 ,  H01S5/024 ,  H01S5/042 ,  H04B10/50 ,  H01L33/64 ,  H04B10/80

Abstract: An optical power transfer device with an embedded active cooling chip is disclosed. The device includes a cooling chip made of a semiconductor material, and a first subassembly and a second subassembly mounted on the cooling chip. The cooling chip comprises at least one metallization layer on a portion of a first surface of the cooling chip, at least one inlet through a second surface of the cooling chip, wherein the second surface is opposite to the first surface, at least one outlet through the second surface and one or more micro-channels extending between and fluidly coupled to the at least one inlet and the at least one outlet. A cooling fluid flows through the one or more micro-channels. The first subassembly is mounted on the at least one metallization layer and comprises a laser. The second subassembly comprises a phototransducer configured to receive a laser beam from the laser.

公开(公告)号：US10178110B2

公开(公告)日：2019-01-08

申请号：US15164792

申请日：2016-05-25

Applicant: Broadcom Corporation

Inventor： Sreenadh Kareti

IPC: G06F21/55 ,  G06F1/32 ,  H04L29/06 ,  G06F1/28 ,  H04W12/12 ,  G06F21/00 ,  H04W52/02 ,  H04W84/18

Abstract: Systems and methods are provided for detecting and mitigating a sleep deprivation attack (SDA). A method for detection of the SDA includes one of tracking power consumption rate of a device, incoming request signals received by the device, or an activity duration of one or more physical interfaces of the device. A system for mitigation of the SDA includes the device to be protected from the SDA, a counter to count request signals received by the device from another device, a counter attack circuit to pose one or more security challenges by sending a request message to the other device once a counted number of request signals exceeds a pre-determined number, and a control circuit to terminate connection with the other device if an expected reply based on the request message is not received from the other device within a pre-determined time duration.

公开(公告)号：US20180041305A1

公开(公告)日：2018-02-08

申请号：US15226545

申请日：2016-08-02

Applicant: BROADCOM CORPORATION

Inventor： Magesh VALLIAPPAN ,  Anand Kumar PATHAK

IPC: H04L1/00 ,  H04L12/26

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L1/0073 ,  H04L25/03 ,  H04L43/0894

Abstract: An electronic device includes circuitry configured to establish a steady-state connection with another device via a communication link. A backchannel data frame is detected in a steady-state data stream received from the other device via the communication link at a first predetermined data rate. The circuitry is configured to modify one or more signal transmission parameters based on signal information included in the backchannel data frame.