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公开(公告)号：US09219147B2
公开(公告)日：2015-12-22
申请号：US14271217
申请日：2014-05-06
发明人： Eng Huat Toh , Jae Gon Lee , Chung Foong Tan , Elgin Quek
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。
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公开(公告)号：US09373674B2
公开(公告)日：2016-06-21
申请号：US14639524
申请日：2015-03-05
发明人： Chang Yong Xiao , Roderick Miller , Jie Chen
IPC分类号： H01L27/06 , H01L27/08 , H01L49/02 , H01L23/522
CPC分类号： H01L28/24 , H01L23/5228 , H01L27/0629 , H01L28/20 , H01L28/22 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL
摘要翻译： 提供了一种用于在MOL工艺中形成夹层镶嵌电阻器的方法以及所得到的器件。 实施例包括在基板上形成包括层间电介质（ILD），第一电介质层和牺牲层（SL）的膜堆叠; 去除所述SL和所述第一介电层的一部分，形成第一空腔; 在第一腔中和SL上保形地形成电阻材料层; 在所述电阻材料层上沉积第二电介质层并填充所述第一腔; 以及去除所述第二电介质层，所述电阻材料层不在所述第一腔中，以及所述SL的至少部分深度
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公开(公告)号：US20140239391A1
公开(公告)日：2014-08-28
申请号：US14271217
申请日：2014-05-06
发明人： Eng Huat TOH , Jae Gon LEE , Chung Foong TAN , Elgin QUEK
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/402 , H01L29/42368 , H01L29/495 , H01L29/4983 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/66681
摘要： An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.
摘要翻译： LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。
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公开(公告)号：US20130339916A1
公开(公告)日：2013-12-19
申请号：US13527196
申请日：2012-06-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation.
摘要翻译： 公开了一种基于SOC设计的拓扑和/或密度在SOC设计中选择和放置IP块的方法。 实施例包括：显示用户界面; 至少部分地在用户界面中呈现包括IP块的SOC设计的拓扑和密度视图; 以及在基于所述呈现的所述SOC设计中针对所述SOC设计的所述IP块的拓扑和/或密度转换之前进行修改。
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公开(公告)号：US20120292735A1
公开(公告)日：2012-11-22
申请号：US13112317
申请日：2011-05-20
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/088
摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
摘要翻译： 形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。 实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。 实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。
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