公开(公告)号：US08706923B2

公开(公告)日：2014-04-22

申请号：US12881614

申请日：2010-09-14

Applicant: Jagadeesh Sankaran ,  Jeremiah E. Golston

Inventor： Jagadeesh Sankaran ,  Jeremiah E. Golston

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information.

Abstract translation: 根据至少一些实施例，系统包括配置成运行多个线程的处理实体。 该系统还包括耦合到该处理实体的直接存储器访问（DMA）引擎，该DMA引擎被配置为跟踪多个DMA通道中的每一个的DMA空中状态信息。 所述处理实体被配置为基于所述DMA在飞行状态信息来管理与DMA引擎的DMA通道的重叠的DMA请求。

公开(公告)号：US08134401B2

公开(公告)日：2012-03-13

申请号：US12729066

申请日：2010-03-22

Applicant: Bradford Lawrence Hunter ,  Wallace Edward Matthews

Inventor： Bradford Lawrence Hunter ,  Wallace Edward Matthews

IPC: G06F7/64 ,  G06G7/18 ,  G06G7/19

CPC classification number: H03K5/24

Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.

Abstract translation: 所公开的低失调开关电容器比较器的系统和方法减少了建立误差。 该系统分两大步骤。 在第一阶段期间，输入电压在输入电容器上进行采样，差分放大器配置为单位增益配置以对放大器偏移进行采样。 在第二阶段期间，输入电压差在比较器的输出端被放大。 通过在第二阶段开始时短路差分放大器的短路时段的输出来减小放大器瞬态采样误差。 差分放大器的输出端的时钟比较器提供了使用内部正反馈的快速比较。 差分放大器应该已经开发出足够的差分输出电压来克服时钟比较器的偏移。

公开(公告)号：US06979899B2

公开(公告)日：2005-12-27

申请号：US10749610

申请日：2003-12-31

Applicant: Darvin R. Edwards

Inventor： Darvin R. Edwards

IPC: H01L23/12 ,  H01L23/36 ,  H01L23/42

CPC classification number: H01L23/42 ,  H01L23/36 ,  H01L2924/15311 ,  H01L2924/16153

Abstract: A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die mounted on a substrate. A conductive layer is deposited in the at least one cavity that substantially fills the space between the at least one cavity and the at least one die when the lid is coupled to the substrate.

公开(公告)号：US4660155A

公开(公告)日：1987-04-21

申请号：US633388

申请日：1984-07-23

Applicant: Robert C. Thaden ,  Jeffrey C. Bond

Inventor： Robert C. Thaden ,  Jeffrey C. Bond

IPC: G09G1/16 ,  G09G5/00 ,  G09G5/393 ,  G06F3/14 ,  G06F15/62

CPC classification number: G09G5/001 ,  G09G5/393 ,  G09G2360/126

Abstract: A video system has a controller for controlling the transfer of data from a processor to a CRT monitor. The controller has two clocks and a CRT interface for synchronously interfacing the controller to the CRT monitor, a second interface for synchronously interfacing the controller to the processor. A first clock source provides timing for the CRT interface and is in synch with the timing of the CRT monitor. A second clock source provides timing for the processor interphase which is in synch with the timing of the processor.

Abstract translation: 视频系统具有用于控制从处理器到CRT监视器的数据传送的控制器。 控制器具有两个时钟和一个CRT接口，用于将控制器同步地连接到CRT监视器，第二接口用于将控制器同步地连接到处理器。 第一个时钟源为CRT接口提供定时，并与CRT显示器的时序同步。 第二个时钟源提供与处理器的时序同步的处理器中间时序。

公开(公告)号：US10750645B2

公开(公告)日：2020-08-18

申请号：US16218468

申请日：2018-12-12

Applicant: Texas Instruments Incorporated

Inventor： John Charles Ehmke ,  Scott Patrick Overmann ,  Sean Christopher O'Brien

IPC: G02F1/1333 ,  G02B27/01 ,  H05K7/20 ,  B60K35/00

Abstract: In described examples, an image-generating panel is arranged for modulating a projection beam to include a modulated optical image. A cooling device is arranged to transfer heat received from the image-generating panel to a heat sink. The cooling device is arranged to receive the projection beam on a first side and to transmit the projection beam from a second side. The heat received from the image-generating panel can include heat generated by the image-generating panel in response to incidental sunlight.

公开(公告)号：US20140346887A1

公开(公告)日：2014-11-27

申请号：US14050984

申请日：2013-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： BHARADVAJ BHAMIDIPATI ,  SWAMINATHAN SANKARAN ,  MARK W. MORGAN ,  GREGORY E. HOWARD ,  BRADLEY A. KRAMER

IPC: H04B5/00

CPC classification number: H02J50/12 ,  H02J50/23 ,  H04B5/005 ,  H04B5/0087

Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.

Abstract translation: 封装上的系统（SOP）可以包括电隔离器。 电流隔离器可以包括输入级，其被配置为响应于接收到输入调制信号而发送输入RF信号。 电流隔离器还可以包括通过电介质与输入级电隔离的谐振耦合器。 谐振耦合器可以被配置为对输入的RF信号进行滤波，并响应输入的RF信号传输输出的RF信号。 电流隔离器还可以包括通过电介质与谐振耦合器电隔离的输出级。 输出级可以被配置为响应于接收输出RF信号而提供输出调制信号。

公开(公告)号：US10833663B2

公开(公告)日：2020-11-10

申请号：US16509526

申请日：2019-07-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Schultz ,  Robert Callaghan Taft

IPC: H03K5/156 ,  H03K5/135 ,  H03K5/04

Abstract: A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.

公开(公告)号：US09118342B2

公开(公告)日：2015-08-25

申请号：US14033047

申请日：2013-09-20

Applicant: Texas Instruments Incorporated

Inventor： Vikas Singh ,  Anand Kannan ,  Ashish Lachhwani

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/46

CPC classification number: H03M3/372 ,  H03M1/002 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/454

Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Abstract translation: 具有输入级和输出级的Δ-Σ调制器。 输入级接收模拟输入信号和第一数模转换器（DAC）的输出。 输入级产生处理后的误差信号。 附加求和装置接收处理的误差信号。 输出级接收附加求和装置的输出并产生延迟的数字输出信号。 差分器和第一个数模转换器（DAC）接收延迟的数字输出信号作为反馈信号。 第二DAC接收微分器的输出，并向另外的负反馈系数乘法器提供输出。 附加求和装置接收附加负反馈系数乘法器的输出。

公开(公告)号：US08111731B2

公开(公告)日：2012-02-07

申请号：US12061878

申请日：2008-04-03

Applicant: Zukang Shen ,  Tarik Muharemovic

Inventor： Zukang Shen ,  Tarik Muharemovic

IPC: H04B1/00

CPC classification number: H04L5/0019

Abstract: A method of transmitting signals in a communication system over at least two time periods including generating a base signal comprising of at least two samples in each time period, selecting a scrambling sequence of length equal to or greater than the number of time periods, scaling all samples in said signal in a time period with one element of said scrambling sequence and transmitting the scaled signal in said time period. Different elements of the scrambling sequence are used to scale the base signal in different time periods. The signal in each time period is obtained by scaling a base signal. The scrambling sequence is preferably a pseudo-random sequence. The step of scaling all samples in said signal in a time period consists of multiplying all samples of said signal with an element of said scrambling sequence.

Abstract translation: 一种在至少两个时间段内在通信系统中发送信号的方法，包括在每个时间周期内生成包括至少两个采样的基本信号，选择长度等于或大于时间周期数的加扰序列， 在所述信号中采用所述加扰序列的一个元素在所述信号中采样，并在所述时间周期内发送经缩放的信号。 加扰序列的不同元素用于在不同时间段内缩放基本信号。 通过缩放基本信号来获得每个时间段中的信号。 扰频序列优选地是伪随机序列。 在一段时间内缩放所述信号中的所有采样的步骤包括将所述信号的所有样本与所述加扰序列的元素相乘。

公开(公告)号：US20110058246A1

公开(公告)日：2011-03-10

申请号：US12945171

申请日：2010-11-12

Applicant: Joshua J. Malone

Inventor： Joshua J. Malone

IPC: G02B26/00

CPC classification number: B81C1/00333 ,  G02B26/0841 ,  H01L21/481

Abstract: A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method of forming and utilizing a package that exposes regions of an alignment reference plane. The device within the package is mounted on the reference plane such that the exposed regions allow precise alignment with the device in a direction perpendicular to the reference plane. Alignment surfaces formed in a display system or other system contact the reference plane at the exposed regions to position the packaged device relative to other components of the system. One embodiment of the package 400 taught has laminated layers forming the package substrate 402 and providing a precision reference plane 416 relative to the position of the micromirror device 404. The package may be formed by laminating several layers of material in sheets to form several package substrates simultaneously. Voids formed in the layers 408 on one side of the reference plane provide access to the reference plane. A transparent cover or lid 412 is attached to the package substrate 402 sealing the micromirror 404 in the cavity 410. The preceding abstract is submitted with the understanding that it only will be used to assist in determining, from a cursory inspection, the nature and gist of the technical disclosure as described in 37 C.F.R. §1.72(b). In no case should this abstract be used for interpreting the scope of any patent claims.

Abstract translation: 将微镜阵列与微镜组件和微镜组件对准到显示系统的系统和方法。 一个实施例提供了一种形成和利用暴露对准参考平面的区域的封装的方法。 封装内的器件安装在参考平面上，使得暴露区域允许在垂直于参考平面的方向上与器件精确对准。 形成在显示系统或其他系统中的对准表面在暴露区域处接触参考平面以相对于系统的其它部件定位封装的装置。 所教导的封装400的一个实施例具有形成封装衬底402的层压层，并且相对于微反射镜器件404的位置提供精确的参考平面416.封装可以通过将片材中的多层材料层叠以形成多个封装衬底 同时。 在参考平面一侧的层408中形成的空隙提供对参考平面的访问。 将透明盖或盖412连接到封装基板402上，密封空腔410中的微镜404.前面的摘要被提交，理解是它仅用于帮助从粗略检查来确定自然和要点 的37 CFR中描述的技术披露 §1.72（b）。 在任何情况下，本摘要不得用于解释任何专利权利要求的范围。