公开(公告)号：US10394567B2

公开(公告)日：2019-08-27

申请号：US15825418

申请日：2017-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Hugh Shen ,  Derek E. Williams

IPC: G11C11/406 ,  G06F9/38 ,  G06F9/54 ,  G06F9/30 ,  G06F12/08

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

公开(公告)号：US09665297B1

公开(公告)日：2017-05-30

申请号：US15333851

申请日：2016-10-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Luis E. De La Torre ,  Bernard C. Drerup ,  Sanjeev Ghai ,  Guy L. Guthrie ,  Alexander M. Taft ,  Derek E. Williams

IPC: G06F3/06 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/1044

Abstract: A processor core is supported by an upper level cache and a lower level cache that receives, from an interconnect fabric, a write injection request requesting injection of a partial cache line of data into a target cache line identified by a target real address. In response to receipt of the write injection request, a determination is made that the upper level cache is a highest point of coherency for the target real address. In response to the determination, the upper level cache and lower level cache collaborate to transfer the target cache line from the upper level cache to the lower level cache. The lower level cache updates the target cache line by merging the partial cache of data into the target cache line and storing the updated target cache line in the lower level cache.

公开(公告)号：US09032157B2

公开(公告)日：2015-05-12

申请号：US13711004

申请日：2012-12-11

Applicant: International Business Machines Corporation

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Geraint North ,  William J. Starke ,  Phillip G. Williams

IPC: G06F12/12 ,  G06F9/455 ,  G06F12/08 ,  G06F11/00

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/202 ,  G06F11/2041 ,  G06F11/2097 ,  G06F12/0891 ,  G06F2009/45583

Abstract: Disclosed is a computer system (100) comprising a processor unit (110) adapted to run a virtual machine in a first operating mode; a cache (120) accessible to the processor unit, said cache comprising a plurality of cache rows (1210), each cache row comprising a cache line (1214) and an image modification flag (1217) indicating a modification of said cache line caused by the running of the virtual machine; and a memory (140) accessible to the cache controller for storing an image of said virtual machine; wherein the processor unit comprises a replication manager adapted to define a log (200) in the memory prior to running the virtual machine in said first operating mode; and said cache further includes a cache controller (122) adapted to periodically check said image modification flags; write only the memory address of the flagged cache lines in the defined log and subsequently clear the image modification flags. A computer cluster including such computer systems and a method of managing such a computer cluster are also disclosed.

Abstract translation: 公开了一种包括适于以第一操作模式运行虚拟机的处理器单元（110）的计算机系统（100） 所述高速缓存包括多个高速缓存行（1210），每个高速缓存行包括高速缓存行（1214）和指示所述高速缓存行的修改的图像修改标志（1217），所述高速缓存行指示由 虚拟机的运行; 以及高速缓存控制器可访问的存储器（140），用于存储所述虚拟机的图像; 其中所述处理器单元包括适于在所述第一操作模式中运行所述虚拟机之前在所述存储器中定义日志（200）的复制管理器; 并且所述高速缓存还包括适于周期性地检查所述图像修改标志的高速缓存控制器（122） 只写入定义的日志中标记的高速缓存行的存储器地址，然后清除映像修改标志。 还公开了包括这种计算机系统的计算机集群和管理这种计算机集群的方法。

公开(公告)号：US20150127910A1

公开(公告)日：2015-05-07

申请号：US14170172

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0811

Abstract: A technique for operating a data processing system includes determining whether a cache line that is to be victimized from a cache includes high availability (HA) data that has not been logged. In response determining that the cache line that is to be victimized from the cache includes HA data that has not been logged, an address for the HA data is written to an HA dirty address data structure, e.g., a dirty address table (DAT), in a first memory via a first non-blocking channel. The cache line that is victimized from the cache is written to a second memory via a second non-blocking channel.

Abstract translation: 一种用于操作数据处理系统的技术包括确定要从高速缓存受害的高速缓存行是否包括尚未记录的高可用性（HA）数据。 响应于确定要从缓存中受害的高速缓存线包括尚未记录的HA数据，HA数据的地址被写入HA脏地址数据结构，例如脏地址表（DAT）， 经由第一非阻塞通道在第一存储器中。 从缓存中受害的高速缓存线经由第二非阻塞通道被写入第二存储器。

公开(公告)号：US20150127906A1

公开(公告)日：2015-05-07

申请号：US14073553

申请日：2013-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存的散步以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US10394566B2

公开(公告)日：2019-08-27

申请号：US15615313

申请日：2017-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  Hugh Shen ,  Derek E. Williams

IPC: G11C11/406 ,  G06F9/38 ,  G06F9/54 ,  G06F9/30 ,  G06F12/08

Abstract: A data processing system includes a plurality of processor cores each having a respective store-through upper level cache and a store-in banked lower level cache. Store requests of the plurality of processor cores destined for the banked lower level cache are buffered in multiple store queues including a first store queue and a second store queue. In response to determining that the multiple store queues contain store requests targeting a common bank of the banked lower level cache, store requests from the first store queue are temporarily favored for selection for issuance to the banked lower level cache over those in the second store queue.

公开(公告)号：US20150127909A1

公开(公告)日：2015-05-07

申请号：US14170106

申请日：2014-01-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Hien Minh Le ,  Hugh Shen ,  Philip G. Williams

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F11/14 ,  G06F11/141 ,  G06F11/1484 ,  G06F11/2023 ,  G06F11/2097 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1016

Abstract: A technique for operating a high-availability (HA) data processing system includes, in response to receiving an HA logout indication at a cache, initiating a walk of the cache to locate cache lines in the cache that include HA data. In response to determining that a cache line includes HA data, an address of the cache line is logged in a first portion of a buffer in the cache. In response to the first portion of the buffer reaching a determined fill level, contents of the first portion of the buffer are logged to another memory. In response to all cache lines in the cache being walked, the cache walk is terminated.

Abstract translation: 用于操作高可用性（HA）数据处理系统的技术包括响应于在高速缓存处接收到HA注销指示，启动高速缓存行走以定位包括HA数据的高速缓存中的高速缓存行。 响应于确定高速缓存行包括HA数据，高速缓存行的地址被记录在高速缓存中的缓冲器的第一部分中。 响应于缓冲器的第一部分达到确定的填充级别，缓冲器的第一部分的内容被记录到另一个存储器。 响应缓存中的所有缓存行被行走，高速缓存行走终止。

公开(公告)号：US08930629B2

公开(公告)日：2015-01-06

申请号：US13655833

申请日：2012-10-19

Applicant: International Business Machines Corporation

Inventor： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0817 ,  G06F12/0804 ,  G06F12/121 ,  G06F12/122 ,  G06F12/126

Abstract: In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.

Abstract translation: 响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。 作为响应，确定目标地址是否在较低级别高速缓存中。 如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐 在包含目标缓存行的同余类中。 响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

公开(公告)号：US20230222066A1

公开(公告)日：2023-07-13

申请号：US17572245

申请日：2022-01-10

Applicant: International Business Machines Corporation

Inventor： Mohit Karve ,  Naga P. Gorti ,  Guy L. Guthrie ,  Sanjeev Ghai

IPC: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804

CPC classification number: G06F12/0862 ,  G06F12/0871 ,  G06F12/0817 ,  G06F12/0804 ,  G06F2212/1021

Abstract: A method, programming product, processor, and/or system for prefetching data is disclosed that includes: receiving a request for data at a cache; identifying whether the request for data received at the cache is a demand request or a prefetch request; and determining, in response to identifying that the request for data received at the cache is a prefetch request, whether to terminate the prefetch request, wherein determining whether to terminate the prefetch request comprises: determining how many hits have occurred for a prefetch stream corresponding to the prefetch request received at the cache; and determining, based upon the number of hits that have occurred for the prefetch stream corresponding to the prefetch request received by the cache, whether to terminate the prefetch request.

公开(公告)号：US11354243B1

公开(公告)日：2022-06-07

申请号：US16950511

申请日：2020-11-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Derek E. Williams ,  Guy L. Guthrie ,  Hugh Shen ,  Sanjeev Ghai ,  Luke Murray

IPC: G06F12/08 ,  G06F13/40 ,  G06F9/30 ,  G06F12/0815 ,  G06F30/327 ,  G06F30/33

Abstract: A processing unit for a data processing system includes a processor core that issues memory access requests and a cache memory coupled to the processor core. The cache memory includes a reservation circuit that tracks reservations established by the processor core via load-reserve requests and a plurality of read-claim (RC) state machines for servicing memory access requests of the processor core. The cache memory, responsive to receipt from the processor core of a store-conditional request specifying a store target address, allocates an RC state machine among the plurality of RC state machines to process the store-conditional request and transfers responsibility for tracking a reservation for the store target address from the reservation circuit to the RC state machine.