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公开(公告)号：US12057976B2
公开(公告)日：2024-08-06
申请号：US18363424
申请日：2023-08-01
Applicant: Kandou Labs, S.A.
Inventor： Brian Holden , Amin Shokrollahi
CPC classification number: H04L25/4917 , B41J2/00 , H03M5/145 , H04J13/12 , H04J13/16 , H04L1/00 , H04L1/0041 , H04L25/02 , H04L25/0272 , H04L25/49 , H04L25/4906
Abstract: Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
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公开(公告)号：US20190363916A1
公开(公告)日：2019-11-28
申请号：US16533592
申请日：2019-08-06
Applicant: Kandou Labs, S.A.
Inventor： Amin Shokrollahi , Brian Holden , Richard Simpson
Abstract: Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.
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公开(公告)号：US20180091351A1
公开(公告)日：2018-03-29
申请号：US15829904
申请日：2017-12-02
Applicant: KANDOU LABS, S.A.
Inventor： Brian Holden , Amin Shokrollahi
IPC: H04L27/26 , G06F13/42 , G11C7/10 , G11C11/4093 , G11C7/22 , G11C11/4076
CPC classification number: H04L27/2637 , G06F13/426 , G11C7/1006 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C11/4076 , G11C11/4093 , H04L25/4919 , Y02D10/14 , Y02D10/151
Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
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4.发明申请公开(公告)号：US20180076912A1
公开(公告)日：2018-03-15
申请号：US15816941
申请日：2017-11-17
Applicant: KANDOU LABS, S.A.
Inventor： Brian Holden , Amin Shokrollahi , Anant Singh
IPC: H04B17/364 , H04B3/00 , H04L25/49 , H04L25/02 , H04B3/02 , H04L1/06 , H04L7/04 , H04L25/08 , H04B5/00 , H04L25/03
CPC classification number: H04B17/364 , G06F13/00 , H04B3/00 , H04B3/02 , H04B5/0031 , H04B5/0081 , H04L1/0041 , H04L1/0643 , H04L7/043 , H04L7/048 , H04L25/0268 , H04L25/0272 , H04L25/028 , H04L25/0292 , H04L25/03019 , H04L25/08 , H04L25/4925 , H04L2001/0096 , Y02D70/26 , Y02D70/42
Abstract: Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.
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公开(公告)号：US09838017B2
公开(公告)日：2017-12-05
申请号：US15176084
申请日：2016-06-07
Applicant: Kandou Labs, S.A.
Inventor： John Fox , Brian Holden , Peter Hunt , John D. Keay , Amin Shokrollahi , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich , Richard Simpson
IPC: H03K19/01 , H03K19/0185 , H04B1/40 , H04L29/08 , H01L23/538 , H03K19/0175 , G06F13/42 , H03K3/037 , H01L23/14
CPC classification number: H03K19/018521 , G06F13/4282 , H01L23/147 , H01L23/5384 , H01L2224/16 , H01L2924/15174 , H01L2924/15192 , H03K3/037 , H03K19/017509 , H04B1/40 , H04L67/12 , Y02D10/14 , Y02D10/151
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.
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Patent Agency Ranking
公开(公告)号：US09607673B1
公开(公告)日：2017-03-28
申请号：US14974698
申请日：2015-12-18
Applicant: Kandou Labs S.A.
Inventor： John Fox , Brian Holden , Amin Shokrollahi , Anant Singh , Giuseppe Surace
CPC classification number: G11C7/22 , G06F13/1689 , G06F13/385 , G06F13/4243 , G11C7/10 , G11C7/1072 , G11C8/10
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.
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公开(公告)号：US09596109B2
公开(公告)日：2017-03-14
申请号：US14253584
申请日：2014-04-15
Applicant: Kandou Labs, S.A.
Inventor： John Fox , Brian Holden , Ali Hormati , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich
CPC classification number: H04L25/085 , H03M5/04 , H03M5/16 , H03M13/31 , H04L1/0041 , H04L1/0057 , H04L25/0272 , H04L25/03057 , H04L25/03885 , H04L2001/0094
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.
Abstract translation: 描述了用于通过物理信道发送数据的系统和方法，以在低功率利用率的高速运行的发送设备和接收设备之间提供高带宽，低延迟的接口。 使用矢量信令代码，使用组合信令对四条线路进行通信，其中一组的每条线路携带可能采用四个信号值之一的低摆幅信号。 公开了用于组信令通信的优选特征的线组的拓扑和设计。
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公开(公告)号：US09362974B2
公开(公告)日：2016-06-07
申请号：US14823870
申请日：2015-08-11
Applicant: KANDOU LABS S.A.
Inventor： John Fox , Brian Holden , Peter Hunt , John D. Keay , Amin Shokrollahi , Andrew Kevin John Stewart , Giuseppe Surace , Roger Ulrich , Richard Simpson
IPC: H04B1/40 , H04L29/08 , H03K19/0175 , H03K19/0185 , H01L23/14 , H01L23/538
CPC classification number: H03K19/018521 , G06F13/4282 , H01L23/147 , H01L23/5384 , H01L2224/16 , H01L2924/15174 , H01L2924/15192 , H03K3/037 , H03K19/017509 , H04B1/40 , H04L67/12 , Y02D10/14 , Y02D10/151
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.
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公开(公告)号：US09362947B2
公开(公告)日：2016-06-07
申请号：US14823866
申请日：2015-08-11
Applicant: KANDOU LABS S.A.
Inventor： Harm Cronie , Brian Holden
CPC classification number: H03M7/00 , G06F11/1072 , G06F12/0207 , H03M1/18 , Y02D10/13
Abstract: A sorting decoder captures the rank-order of a set of input analogue signals in the digital domain using simple logic components such as self-timed first state elements, without requiring conventional analogue-to-digital signal converters. The analogue signals are each compared against a monotonic dynamic reference and the resulting comparisons are snapshot by a self-timed first state element for each input signal, or the last member of a sorted collection of input signals, at the time when it reaches the reference signal, so that a different snapshot representing the signal value ranking relative to the other signal values is produced for each input signal. The resulting rank-order estimation snapshots are binary signals that can then be further processed by a simple sorting logic circuit based on elementary logic components.
Abstract translation: 排序解码器使用诸如自定时第一状态元素之类的简单逻辑元件捕获数字域中的一组输入模拟信号的秩次，而不需要常规的模数转换器。 模拟信号各自与单调动态参考进行比较，并且所得到的比较是对于每个输入信号的自定时第一状态元素或输入信号的排序集合的最后一个成员在到达参考时的快照 信号，使得针对每个输入信号产生表示相对于其它信号值排列的信号值的不同快照。 所得到的秩序估计快照是二进制信号，然后可以通过基于基本逻辑分量的简单分类逻辑电路进一步处理二进制信号。
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10.发明授权公开(公告)号：US09357036B2
公开(公告)日：2016-05-31
申请号：US14842511
申请日：2015-09-01
Applicant: Kandou Labs, S.A.
Inventor： John Fox , Brian Holden , Peter Hunt , John D. Keay , Amin Shokrollahi , Richard Simpson , Anant Singh , Andrew Kevin John Stewart , Giuseppe Surace
CPC classification number: H04L25/4906 , G06F13/426 , H03M5/16 , H03M5/20 , H04L25/0272 , H04L25/4917 , H04L25/493 , H04L69/04 , Y02D10/14 , Y02D10/151
Abstract: Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices with significantly reduced or eliminated Simultaneous Switching Output noise. Controller-side and memory-side embodiments of such channel interfaces are disclosed which do not require additional pin count or data transfer cycles, have low power utilization, and introduce minimal additional latency. In some embodiments of the invention, three or more voltage levels are used for signaling.
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