公开(公告)号：US20250044966A1

公开(公告)日：2025-02-06

申请号：US18362796

申请日：2023-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Nicholas Carmine DeFiore ,  Sridhar Varadharajulu Gada ,  James R. Magro ,  Michael L. Choate ,  Wayne Paul Rodrigue ,  NrusimhaVamsi Krishna Godavarti ,  Robert Gentile ,  Roozbeh Paribakht ,  Anwar Kashem

IPC: G06F3/06

Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US10985097B2

公开(公告)日：2021-04-20

申请号：US16048630

申请日：2018-07-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Fei Guo ,  Feng Zhu ,  Julius Din ,  Anwar Kashem ,  Sally Yeung

IPC: B23P19/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/50

Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

公开(公告)号：US20180337119A1

公开(公告)日：2018-11-22

申请号：US16048630

申请日：2018-07-30

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Fei Guo ,  Feng Zhu ,  Julius Din ,  Anwar Kashem ,  Sally Yeung

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/14

CPC classification number: H01L23/49822 ,  H01L23/147 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  Y10T29/49082

Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.

公开(公告)号：US20240295898A1

公开(公告)日：2024-09-05

申请号：US18663864

申请日：2024-05-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Deepesh John

IPC: G06F1/08 ,  H03K5/00 ,  H03K5/22

CPC classification number: G06F1/08 ,  H03K5/22 ,  H03K2005/00286

Abstract: Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

公开(公告)号：US11947833B2

公开(公告)日：2024-04-02

申请号：US17845922

申请日：2022-06-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani ,  Tsun Ho Liu

IPC: G06F3/06 ,  G06F18/214

CPC classification number: G06F3/0656 ,  G06F3/0683 ,  G06F18/214 ,  G06F3/0604

Abstract: A method and apparatus for training data in a computer system includes reading data stored in a first memory address in a memory and writing it to a buffer. Training data is generated for transmission to the first memory address. The data is transmitted to the first memory address. Information relating to the training data is read from the first memory address and the stored data is read from the buffer and written to the memory area where the training data was transmitted.

公开(公告)号：US20230205433A1

公开(公告)日：2023-06-29

申请号：US17565372

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0655

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

公开(公告)号：US12079490B2

公开(公告)日：2024-09-03

申请号：US17565372

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0673

Abstract: Methods and systems are disclosed for frequency transitioning in a memory interface system. Techniques disclosed include receiving a signal indicative of a change in operating frequency, into a new frequency, in a processing unit interfacing with memory via the memory interface system; switching the system from a normal mode of operation into a transition mode of operation; updating control and state register (CSR) banks of respective transceivers of the system through a mission bus used during the normal mode of operation; and operating the system in the new frequency.

公开(公告)号：US11875875B2

公开(公告)日：2024-01-16

申请号：US17564426

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C7/22 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/222 ,  G11C5/06 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1093

Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

公开(公告)号：US20230207038A1

公开(公告)日：2023-06-29

申请号：US17564327

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Kashem ,  Craig Daniel Eaton ,  Pouya Najafi Ashtiani

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/36

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/1201 ,  G11C29/36

Abstract: Methods and systems are disclosed for training, by a sequencer of a memory interface system, an interface with DRAM. Techniques disclosed comprise scheduling a command sequence, including DRAM commands that are interleaved with one or more CSR commands; executing the scheduled command sequence, wherein the DRAM commands are sent to the DRAM through an internal datapath of the system and the CSR commands are sent to the internal datapath; and training the interface based on exchange of data, carried out by the DRAM commands, including adjustments to an operational parameter associated with the interface.

公开(公告)号：US20150378603A1

公开(公告)日：2015-12-31

申请号：US14318114

申请日：2014-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Glenn A. Dearth ,  Gerry Talbot ,  Anwar Kashem ,  Edoardo Prete ,  Brian Amick

IPC: G06F3/06

CPC classification number: G06F13/4072 ,  G06F13/1689

Abstract: A controller integrated in a memory physical layer interface (PHY) can be used to control training used to configure the memory PHY for communication with an associated external memory such as a dynamic random access memory (DRAM), thereby removing the need to provide training sequences over a data pipeline between a BIOS and the memory PHY. For example, a controller integrated in the memory PHY can control read training and write training of the memory PHY for communication with the external memory based on a training algorithm. The training algorithm may be a seedless training algorithm that converges on a solution for a timing delay and a voltage offset between the memory PHY and the external memory without receiving, from a basic input/output system (BIOS), seed information that characterizes a signal path traversed by training sequences or commands generated by the training algorithm.

Abstract translation: 集成在存储器物理层接口（PHY）中的控制器可用于控制用于配置存储器PHY的训练以与诸如动态随机存取存储器（DRAM）的相关联的外部存储器进行通信，由此消除提供训练序列的需要 在BIOS和存储器PHY之间的数据流水线上。 例如，集成在存储器PHY中的控制器可以基于训练算法来控制用于与外部存储器通信的存储器PHY的读取训练和写入训练。 训练算法可以是无核训练算法，其收敛于存储器PHY和外部存储器之间的定时延迟和电压偏移的解，而不从基本输入/输出系统（BIOS）接收表征信号的种子信息 由训练序列生成的训练序列或命令所遍历的路径。