公开(公告)号：US12111769B2

公开(公告)日：2024-10-08

申请号：US17630453

申请日：2021-03-16

申请人： Micron Technology, Inc.

发明人： Xing Wang ,  Zhen Gu ,  Xu Zhang ,  Liping Xu

IPC分类号： G06F12/0873

CPC分类号： G06F12/0873

摘要： Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

公开(公告)号：US20240232093A1

公开(公告)日：2024-07-11

申请号：US18094401

申请日：2023-01-09

申请人： Silicon Motion, Inc.

发明人： Jie-Hao Lee ,  Chien-Cheng Lin ,  Chang-Chieh Huang

IPC分类号： G06F12/0873 ,  G06F12/02

CPC分类号： G06F12/0873 ,  G06F12/0253

摘要： A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table search and associated apparatus are provided. The method may include: utilizing a memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, perform the unbalanced table search to receive a set of first data and a set of second data with first and second active blocks according to first and second commands among the host commands, respectively, and update first and second temporary physical-to-logical (P2L) address mapping tables; and selectively updating a first P2L address mapping table and a second P2L address mapping table according to the first temporary P2L address mapping table and the second temporary P2L address mapping table, respectively, for performing subsequent processing.

公开(公告)号：US11989450B2

公开(公告)日：2024-05-21

申请号：US17415664

申请日：2019-12-20

申请人： Micron Technology, Inc.

发明人： Dmitri A. Yudanov ,  Shanky Kumar Jain

IPC分类号： G06F3/06 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/22 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F9/546 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0873 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1045 ,  G11C7/08 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/08 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4096 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/72 ,  G06F2212/7201

摘要： Methods, systems, and devices related to signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may also include a controller configured to determine whether data associated with an address of the memory array is stored in one or more cache blocks of the signal development cache. As an example, the memory device may determine whether the data is stored in one or more cache blocks of the signal development cache based on mapping information associated with the address of the memory array.

公开(公告)号：US11989311B2

公开(公告)日：2024-05-21

申请号：US17470262

申请日：2021-09-09

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

发明人： Hironori Nakanishi ,  Kana Furuhashi

IPC分类号： H04L9/08 ,  G06F12/14 ,  G06F21/60 ,  G06F21/78 ,  G06F12/0873 ,  H04L9/16

CPC分类号： G06F21/602 ,  G06F12/1408 ,  G06F12/1425 ,  G06F21/78 ,  H04L9/0861 ,  H04L9/0891

摘要： According to one embodiment, a magnetic disk device includes a disk, a head writing data to the disk and reading data from the disk, and a controller managing a key generation of a cryptographic key, based on generation confirmation information which is generated by the cryptographic key managed by an external device and transferred from the external device, and which is unable to generate the cryptographic key.

公开(公告)号：US11954037B2

公开(公告)日：2024-04-09

申请号：US17668803

申请日：2022-02-10

申请人： NVIDIA Corporation

发明人： Ankit Sharma ,  Shridhar Rasal

IPC分类号： G06F12/0873 ,  G06F12/0868 ,  G06F12/0871

CPC分类号： G06F12/0873 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/1044

摘要： A computing system includes a volatile memory, a cache coupled with the volatile memory, and a processing device coupled with the cache and at least one of a storage device or a network port. The processing device is to: generate a plurality of virtual addresses that are sequentially numbered for data that is to be at least one of processed or transferred in response to an input/output (I/O) request; allocate, for the data, a continuous range of physical addresses of the volatile memory; generate a set of hash-based values based on mappings between the plurality of virtual addresses and respective physical addresses of the continuous range of physical addresses; identify a unique cache line of the cache that corresponds to each respective hashed-based value of the set of hash-based values; and cause the data to be directly stored in the unique cache lines of the cache.

公开(公告)号：US20240095179A1

公开(公告)日：2024-03-21

申请号：US18065123

申请日：2022-12-13

申请人： ALIBABA (CHINA) CO., LTD.

发明人： DIMIN NIU ,  YIJIN GUAN ,  TIANCHAN GUAN ,  SHUANGCHEN LI ,  HONGZHONG ZHENG

IPC分类号： G06F12/1009 ,  G06F12/0873 ,  G06F12/122

CPC分类号： G06F12/1009 ,  G06F12/0873 ,  G06F12/122

摘要： A memory management method of a data processing system is provided. The memory management method includes: creating a first memory zone and a second memory zone related to a first node of a first server, wherein the first server is located in the data processing system, and the first node includes a processor and a first memory; mapping the first memory zone to the first memory; and mapping the second memory zone to a second memory of a second server, wherein the second server is located in the data processing system, and the processor is configured to access the second memory of the second server through an interface circuit of the first server and through an interface circuit of the second server.

公开(公告)号：US11907129B2

公开(公告)日：2024-02-20

申请号：US17469971

申请日：2021-09-09

申请人： Sony Interactive Entertainment Inc.

发明人： Hideyuki Saito

IPC分类号： G06F12/0873 ,  G06F12/02

CPC分类号： G06F12/0873 ,  G06F12/0246 ,  G06F2212/1021 ,  G06F2212/463 ,  G06F2212/657 ,  G06F2212/7201

摘要： Disclosed herein is an information processing device including a host unit adapted to request data access by specifying a logical address of a secondary storage device, and a controller adapted to accept the data access request and convert the logical address into a physical address using an address conversion table to perform data access to an associated area of the secondary storage device, in which an address space defined by the address conversion table includes a coarsely granular address space that collectively associates, with logical addresses, physical addresses that are in units larger than those in which data is read.

公开(公告)号：US11907114B2

公开(公告)日：2024-02-20

申请号：US16996810

申请日：2020-08-18

申请人： SMART IOPS, INC.

发明人： Ashutosh Kumar Das ,  Manuel Antonio d'Abreu

IPC分类号： G06F12/02 ,  G06F12/0873 ,  G06F13/16 ,  G06F12/1045

CPC分类号： G06F12/0246 ,  G06F12/0873 ,  G06F12/1045 ,  G06F13/1668 ,  G06F2212/7201

摘要： In certain aspects, dynamic remapping of memory addresses is provided and includes initiating a remapping of a logical block from a “mapped block” to a “remapped block.” Logical address locations for the logical block are mapped to physical address locations in the mapped block. The mapped and remapped blocks include non-volatile memory. A read command is received and determined to be for reading from a logical address location of the logical block, and the logical address location is determined to be mapped to a physical address location. Data is read from the physical address location of the mapped block. A write command is received and determined to be for writing data to the logical address location. Data is written to the physical address location of the remapped block. The read command is received after the initiation of the remapping and before the writing of the data to the remapped block.

公开(公告)号：US11899574B2

公开(公告)日：2024-02-13

申请号：US17965542

申请日：2022-10-13

申请人： Micron Technology, Inc.

发明人： Xiangang Luo ,  Qing Liang

IPC分类号： G06F12/02 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/1045 ,  G06F13/16

CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0873 ,  G06F12/1054 ,  G06F13/1668 ,  G06F2212/7201

摘要： Devices and techniques are disclosed herein for more efficiently performing random write operation for a memory device. In an example, a method of operating a flash memory device can include receiving a write request at a flash memory device from a host, the write request including a first logical block address and write data, saving the write data to a location of the flash memory device having a first physical address, operating the flash memory device in a first mode when an amount of write data associated with the write request is above a threshold, operating the flash memory device in a second mode when an amount of write data is below the threshold, and comparing the amount of write data to the threshold.

公开(公告)号：US11860777B2

公开(公告)日：2024-01-02

申请号：US16930429

申请日：2020-07-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Kyungduk Lee ,  Young-Seop Shim

IPC分类号： G06F12/02 ,  G06F12/0873 ,  G06F12/0882 ,  G06F3/06 ,  G06F11/30

CPC分类号： G06F12/0253 ,  G06F3/0646 ,  G06F11/3037 ,  G06F11/3058 ,  G06F12/0246 ,  G06F12/0873 ,  G06F12/0882

摘要： A memory management method of a storage device including: programming write-requested data in a memory block; counting an elapse time from a time when a last page of the memory block was programmed with the write-requested data; triggering a garbage collection of the storage device when the elapse time exceeds a threshold value; and programming valid data collected by the garbage collection at a first clean page of the memory block.