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815 条记录 (耗时 0.026 秒)

    A DATA PROCESSING APPARATUS AND METHOD FOR HANDLING STALLED DATA
    1.
    发明公开
    A DATA PROCESSING APPARATUS AND METHOD FOR HANDLING STALLED DATA 审中-公开

    公开(公告)号：US20240296132A1

    公开(公告)日：2024-09-05

    申请号：US18574277

    申请日：2022-06-21

    申请人： Arm Limited

    发明人： Mbou Eyole ,  Giacomo Gabrielli ,  Balaji Venu

    IPC分类号： G06F13/16 ,  G06F13/26

    CPC分类号： G06F13/1673 ,  G06F13/161 ,  G06F13/26

    摘要： There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing element comprising processing circuitry to perform processing operations and memory control circuitry to perform data transfer operations and to issue data transfer requests for requested data to the network. The memory control circuitry is configured to monitor the network to retrieve the requested data from the network. Each processing element is further provided with local storage circuitry comprising a plurality of local storage sectors to store data associated with the processing operations, and auxiliary memory control circuitry to monitor the network to detect stalled data (S60). The auxiliary memory control circuitry is configured to transfer the stalled data from the network to an auxiliary storage buffer (S66) dynamically selected from amongst the plurality of local storage sectors (S64).

    USB device and data transfer method thereof
    6.
    发明授权
    USB device and data transfer method thereof 有权

    公开(公告)号：US11216398B2

    公开(公告)日：2022-01-04

    申请号：US16801223

    申请日：2020-02-26

    申请人： REALTEK SEMICONDUCTOR CORPORATION

    发明人： Er-Zih Wong ,  Zhen-Ting Huang ,  Shih-Chiang Chu ,  Sung-Kao Liu ,  Chia-Yi Chang

    IPC分类号： G06F13/26 ,  G06F13/16

    摘要： The invention provides a USB device and a data transfer method thereof. The USB device is coupled to a host and transfers at least one packet to the host. The USB device includes a memory, a USB controller, and a transfer management circuit. The memory stores packets. The USB controller is configured to transfer the packets to the host. The transfer management circuit is coupled between the memory and the USB controller and configured to sequentially read the packets from the memory and sequentially transfer the packets to the USB controller, and to perform the following operations: ending the data transfer when a stored content of the memory does not meet a condition for continuing packet transfer; or ending the data transfer when a last transferred packet meets a preset condition and a next packet that follows the last transferred packet does not meet the preset condition.

    Interrupt processing method, master chip, slave chip, and multi-chip system
    7.
    发明授权
    Interrupt processing method, master chip, slave chip, and multi-chip system 有权

    公开(公告)号：US11113098B2

    公开(公告)日：2021-09-07

    申请号：US16697111

    申请日：2019-11-26

    申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.

    发明人： Zhibing Liang ,  Yifan Li ,  Zekai Chen

    IPC分类号： G06F9/30 ,  G06F13/26 ,  G06F9/48 ,  G06F9/38

    摘要： The present disclosure relates to the field of a multi-chip system, and provides an interrupt processing method, a master chip, a slave chip, and a multi-chip system. An interrupt processing method is applied to a master chip and includes: when an interrupt transport request sent by a slave chip through an interrupt line is detected, obtaining all current interrupt requests (irq_s_1-irq_s_N) of the slave chip, the interrupt request (irq_s_1_-irq_s_N) is generated by a first peripheral (4) of the slave chip; obtaining an interrupt subroutine corresponding to each of the interrupt requests (irq_s_1-irq_s_N), and processing the corresponding interrupt request (irq_s_1-irq_s_N) by using the interrupt subroutine. In the embodiments of the present disclosure, all the interrupt requests (irq_s_1-irq_s_N) of the slave chip are mapped to the master chip, so that the interrupt processing flow of the peripheral on the slave chip is simplified.

    MEMORY PROTOCOL WITH COMMAND PRIORITY
    8.
    发明申请
    MEMORY PROTOCOL WITH COMMAND PRIORITY 有权

    公开(公告)号：US20210263867A1

    公开(公告)日：2021-08-26

    申请号：US17315871

    申请日：2021-05-10

    申请人： Micron Technology, Inc.

    发明人： Robert M. Walker

    IPC分类号： G06F13/18 ,  G06F13/26 ,  G06F3/06 ,  G06F12/02

    摘要： The present disclosure includes apparatuses and methods related to a memory protocol with command priority. An example apparatus can execute a command that includes a read identification (RID) number based on a priority assigned to the RID number in a register. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

    Novel RTOS/OS Architecture for Context Switching Without Disabling Interrupts
    9.
    发明申请
    Novel RTOS/OS Architecture for Context Switching Without Disabling Interrupts 有权

    公开(公告)号：US20210089481A1

    公开(公告)日：2021-03-25

    申请号：US16578350

    申请日：2019-09-22

    申请人： Mazen Arakji

    发明人： Mazen Arakji

    IPC分类号： G06F13/26 ,  G06F9/52

    摘要： The present invention is a novel RTOS/OS architecture that changes the fundamental way that context switching is performed. In all prior operating system implementations, context switching required disabling of interrupts. This opens the possibility that data can be lost. This novel approach consists of a context switching method in which interrupts are never disabled. Two implementations are presented. In the first implementation, the cost is a negligible amount of memory. In the second, the cost is only a minimal impact on the context switching time. This RTOS/OS architecture requires specialized hardware. Concretely, an advanced interrupt controller that supports nesting and tail chaining of prioritized interrupts is needed (e.g. the Nested Vectored Interrupt Controller (NVIC) found on many ARM processors). The novel RTOS/OS architecture redefines how task synchronization primitives such as semaphores and mutexes are released. Whereas previous architectures directly accessed internal structures, this architecture does so indirectly by saving information in shared buffers or setting flags, and then activating a low priority software interrupt that subsequently interprets this data and performs all context switching logic. The software interrupt must be set as the single lowest priority interrupt in the system.

    System and Method of Rerouting an Inter-Processor Communication Link Based on a Link Utilization Value
    10.
    发明申请
    System and Method of Rerouting an Inter-Processor Communication Link Based on a Link Utilization Value 审中-公开

    公开(公告)号：US20200320029A1

    公开(公告)日：2020-10-08

    申请号：US16905627

    申请日：2020-06-18

    申请人： Dell Products L.P.

    发明人： Stuart Allen Berke ,  Wade Andrew Butcher

    IPC分类号： G06F13/26 ,  G06F13/42

    摘要： In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communication link interfaces.