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公开(公告)号：US20230412176A1
公开(公告)日：2023-12-21
申请号：US17947845
申请日：2022-09-19
发明人： Praveen RATHEE , Vishnu KALYANAMAHADEVI GOPALAN JAWARLAL , Sanjeeb Kumar GHOSH , Avneesh Singh VERMA
摘要： A system and method to dynamically control a reset signal for an IQ divider are provided. The system includes an IQ divider configured to output a IQ divider output clock; an input configured to receive a reference clock; a failure sensing circuit configured to sense a failure in the IQ divider output clock, the failure sensing circuit including an automatic frequency calibration (AFC) logic; and a control circuit configured to control a reset signal provided to the IQ divider, based on an output of the failure sensing circuit corresponding the failure sensed by the failure sensing circuit.
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公开(公告)号：US20230194694A1
公开(公告)日：2023-06-22
申请号：US18108993
申请日：2023-02-13
发明人： Alessandro PARISI , Andrea CAVARRA , Alessandro FINOCCHIARO , Giuseppe PAPOTTO , Giuseppe PALMISANO
CPC分类号： G01S13/584 , G01S7/4056 , G01S13/931 , H03B5/1212 , H03B5/1228 , H03L7/193 , H03B5/1265 , H03B5/1293 , H03L7/099 , H03L7/101 , H03L7/103 , H03B5/1243
摘要： Disclosed herein is a tunable resonant circuit including an inductance directly electrically connected in series between first and second nodes, a variable capacitance directly electrically connected between the first and second nodes, and a set of switched capacitances coupled between the first and second nodes. The set of switched capacitances includes a plurality of capacitance units, each capacitance unit comprising a first capacitance for that capacitance unit directly electrically connected between the first node and a switch and a second capacitance for the capacitance unit directly electrically connected between the switch and the second node. Control circuitry is configured to receive an input control signal and connected to control the switches of the set of switched capacitances. A biasing circuit is directly electrically connected to the tunable resonance circuit at the first and second nodes.
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公开(公告)号：US10972112B1
公开(公告)日：2021-04-06
申请号：US16857617
申请日：2020-04-24
发明人： Ning Zhang , Yuchun Liu
摘要： Embodiments described herein relate to a 50%-duty-cycle consecutive integer frequency divider and a phase-locked loop circuit having the frequency divider. The frequency divider includes a consecutive integer frequency divider module having a non-50%-duty-cycle, wherein the module receives a clock signal CLK and an input control signal CB and outputs a consecutive frequency division clock signal CLK1 comprising a non-50% duty cycle; a D flip-flop module for receiving the clock signal CLK and the consecutive frequency division clock signal CLK1 and outputting at least one clock signal CLKx; and a logic OR gate module for receiving the consecutive frequency division clock signal CLK1 and the at least one clock signal CLKx, and outputting an output clock signal CLKout comprising a 50% duty cycle.
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公开(公告)号：US10931289B2
公开(公告)日：2021-02-23
申请号：US16536079
申请日：2019-08-08
发明人： Yasuo Satoh
摘要： Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.
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公开(公告)号：US10230381B2
公开(公告)日：2019-03-12
申请号：US15586867
申请日：2017-05-04
申请人： Cavium, LLC
发明人： JingDong Deng , Omer O. Yildirim
IPC分类号： H03K23/00 , H03L7/193 , H03K3/356 , H03K23/44 , H03L7/099 , H03L7/089 , H03L7/081 , H03K3/3562
摘要： A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).
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公开(公告)号：US10110240B1
公开(公告)日：2018-10-23
申请号：US15786362
申请日：2017-10-17
发明人： Yasuo Satoh
摘要： Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.
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公开(公告)号：US20170099059A1
公开(公告)日：2017-04-06
申请号：US15287570
申请日：2016-10-06
发明人： Hua Wang , David Steven Ripley , Brian J. Roll
CPC分类号： H03L7/0992 , H03B1/00 , H03B5/1265 , H03B5/1271 , H03L1/00 , H03L7/099 , H03L7/10 , H03L7/18 , H03L7/187 , H03L7/193
摘要： Apparatus and methods for tuning a voltage controlled oscillator (VCO) are provided. In one aspect, a method of auto-tuning in a phase-locked loop includes generating a VCO clock signal using a VCO coupled to a capacitor array, dividing the VCO clock signal to generate a divided clock signal using a prescaler circuit having a selectable division ratio, controlling a value of the selectable division ratio using a first counter and a second counter of a counter module, generating a phase-frequency detector feedback signal based on a division control signal M and the divided clock signal using the counter module, counting a number of cycles of the divided clock signal that occur during a calibration interval using a cycle counter of a digital processing logic circuit, and determining the value of a capacitor array control signal based on the number of cycles counted during the calibration interval.
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公开(公告)号：US20160314829A1
公开(公告)日：2016-10-27
申请号：US14696685
申请日：2015-04-27
申请人： ARM LIMITED
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/4096 , H03L7/193
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1051 , Y02D10/14
摘要： An integrated circuit device comprises a first data processing element having a first data interface configured to synchronously communicate data according to a first clock signal at a first clock speed, and a second data interface configured to synchronously communicate data at a second clock speed lower than the first clock speed; and a second data processing element configured to operate in response to a second clock signal at the second clock speed and to synchronously communicate data with the first data processing element via the second data interface according to the second clock speed; the first data processing element being configured to derive, from a source clock signal, the first clock signal and the second clock signal; and the first data processing element and the second data processing element each comprising a clock signal interface by which the second clock signal is provided by the first data processing element to the second data processing element.
摘要翻译： 集成电路装置包括第一数据处理元件，其具有第一数据接口，被配置为以第一时钟速度根据第一时钟信号同步地传送数据;以及第二数据接口，被配置为以低于第二时钟速率的第二时钟速率同步地传送数据 第一时钟速度; 以及第二数据处理元件，被配置为响应于第二时钟速度响应于第二时钟信号进行操作，并且根据第二时钟速度经由第二数据接口与第一数据处理元件同步地传送数据; 所述第一数据处理元件被配置为从源时钟信号导出所述第一时钟信号和所述第二时钟信号; 并且第一数据处理元件和第二数据处理元件各自包括时钟信号接口，第二时钟信号由第一数据处理元件提供给第二数据处理元件。
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公开(公告)号：US20160156363A1
公开(公告)日：2016-06-02
申请号：US15014905
申请日：2016-02-03
发明人： TSUNG-HSIEN TSAI
CPC分类号： G04F10/005 , H03L7/085 , H03L2207/18 , H03L2207/50
摘要： A circuit includes a reset circuit, a counter and a comparator. The reset circuit generates a reset signal based on a reference signal and a controlled signal. The reference signal and the controlled signal are to be sent to the TDC for detection of phase difference. The counter counts to a predetermined value associated with the reference signal and the controlled signal, and is reset to an initial value in response to the reset signal. The comparator compares a count from the counter and the predetermined value, and generates a mask signal when a count from the counter equals the predetermined value. The mask signal masks a portion of pulses of the controlled signal from entering the TDC.
摘要翻译： 电路包括复位电路，计数器和比较器。 复位电路基于参考信号和受控信号产生复位信号。 将参考信号和受控信号发送到TDC以检测相位差。 计数器计数到与参考信号和受控信号相关联的预定值，并且响应于复位信号被复位到初始值。 比较器比较来自计数器的计数和预定值，并且当来自计数器的计数等于预定值时产生掩码信号。 屏蔽信号屏蔽受控信号的一部分脉冲进入TDC。
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10.发明授权Semiconductor device, radio communication terminal, and method for controlling semiconductor device 有权半导体装置，无线通信终端以及半导体装置的控制方法公开(公告)号：US09197276B2
公开(公告)日：2015-11-24
申请号：US14083629
申请日：2013-11-19
发明人： Ryo Endo
CPC分类号： H04L7/033 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/193 , H03L2207/50 , H04B1/1036 , H04B1/40
摘要： A semiconductor device according to the present invention includes a PLL circuit, in which the PLL circuit includes: a phase difference detection unit that detects a phase difference between a reference signal and a division signal; a filter that outputs a control signal according to a detection result of the phase difference detection unit; an oscillation unit that outputs an oscillation signal of a frequency according to the control signal; a division unit that divides the oscillation signal to output it as the division signal; a noise intensity detection unit that detects a noise intensity of a predetermined frequency component included in the control signal; and a phase difference adjustment unit that adjusts a phase difference between the reference signal and the division signal based on the noise intensity detected by the noise intensity detection unit.
摘要翻译： 根据本发明的半导体器件包括PLL电路，其中PLL电路包括：相位差检测单元，其检测参考信号和除法信号之间的相位差; 滤波器，其根据所述相位差检测单元的检测结果输出控制信号; 振荡单元，其根据所述控制信号输出频率的振荡信号; 分割单元，其将振荡信号分频，将其输出作为除法信号; 噪声强度检测单元，其检测包括在所述控制信号中的预定频率分量的噪声强度; 以及相位差调整单元，其基于由噪声强度检测单元检测到的噪声强度来调整基准信号与除法信号之间的相位差。
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