公开(公告)号：US12132501B2

公开(公告)日：2024-10-29

申请号：US17895227

申请日：2022-08-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Wonjae Shin ,  Sung-Joon Kim ,  Heedong Kim ,  Minsu Bae ,  Ilwoong Seo ,  Mijin Lee ,  Seung Ju Lee ,  Hyan Suk Lee ,  Insu Choi ,  Kideok Han

IPC分类号： H03M13/19 ,  G06F11/10 ,  G11C5/04 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/00

CPC分类号： H03M13/19 ,  G06F11/10 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1048 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/52 ,  H03M13/611 ,  G11C5/04

摘要： A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US12126357B2

公开(公告)日：2024-10-22

申请号：US18085236

申请日：2022-12-20

申请人： SK hynix Inc.

发明人： Seon Woo Hwang ,  Seong Jin Kim ,  Jung Hwan Ji

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1111 ,  H03M13/6356

摘要： In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

公开(公告)号：US12126356B2

公开(公告)日：2024-10-22

申请号：US18334905

申请日：2023-06-14

申请人： Panasonic Intellectual Property Corporation of America

发明人： Yutaka Murakami

IPC分类号： H03M13/11 ,  H03M13/00 ,  H03M13/23 ,  H03M13/27 ,  H03M13/35 ,  H04L1/00

CPC分类号： H03M13/1102 ,  H03M13/23 ,  H03M13/235 ,  H03M13/2792 ,  H03M13/353 ,  H03M13/6502 ,  H03M13/6516 ,  H04L1/0041

摘要： A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

公开(公告)号：US20240348267A1

公开(公告)日：2024-10-17

申请号：US18134690

申请日：2023-04-14

申请人： Microsoft Technology Licensing, LLC

发明人： Brett K. DODDS ,  Terry M. GRUNZKE

IPC分类号： H03M13/15 ,  H03M13/00

CPC分类号： H03M13/35 ,  H03M13/353 ,  H03M13/356 ,  H03M13/151 ,  H03M13/611

摘要： A memory controller may receive memory data to be stored on a memory. A memory controller may receive metadata related to the memory data. The metadata may be selected from a predetermined list of metadata. A memory controller may identify an encoding polynomial of a plurality of polynomials that is associated with the metadata, each polynomial of the plurality of polynomials associated with different metadata from the predetermined list of metadata. A memory controller may generate a codeword using the encoding polynomial of the plurality of polynomials and the memory data.

公开(公告)号：US20240348265A1

公开(公告)日：2024-10-17

申请号：US18405553

申请日：2024-01-05

申请人： SK Hynix NAND Product Solutions Corp. (dba Solidigm)

发明人： Zion Kwok

IPC分类号： H03M13/09 ,  H03M13/00

CPC分类号： H03M13/095 ,  H03M13/611

摘要： A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.

公开(公告)号：US20240333311A1

公开(公告)日：2024-10-03

申请号：US18128707

申请日：2023-03-30

申请人： VIAVI Solutions Inc.

发明人： Onur DIZDAR ,  Matthew David BROWN ,  Jiancao HOU ,  Chi-ming LEUNG ,  Ata SATTARZADEH HASHEMI ,  Yi Xien YAP

IPC分类号： H03M13/27 ,  H03M13/00 ,  H03M13/13

CPC分类号： H03M13/2778 ,  H03M13/13 ,  H03M13/635

摘要： A device may receive a downlink signal from a base station and may determine an input-output relation of polar encoding based on a vector of the downlink signal. The device may perform an interleaving operation with a matrix and the input-output relation to obtain an interleaved vector and may utilize rate matching with the interleaved vector to determine a scrambling sequence of the downlink signal. The device may utilize a reverse sequence generator with the scrambling sequence to determine a scrambling sequence initialization vector for the scrambling sequence and may perform one or more actions based on the scrambling sequence initialization vector.

公开(公告)号：US12107601B2

公开(公告)日：2024-10-01

申请号：US17733165

申请日：2022-04-29

申请人： SHENZHEN DAPU MICROELECTRONICS CO., LTD.

发明人： Yan Wang ,  Weijun Li

IPC分类号： H03M13/00 ,  G06N3/08 ,  H03M13/03 ,  H03M13/11

CPC分类号： H03M13/033 ,  G06N3/08 ,  H03M13/1102

摘要： A data error correction method, apparatus, device, and readable storage medium are disclosed. The method includes: acquiring target data to be error-corrected; performing error correction on the target data using an error-correcting code to obtain first data; judging whether the performing of the error correction on the target data is successful; responsive to the performing of the error correction on the target data being not successful, correcting the target data using a target neural network to obtain second data, determining the second data as the target data, and continuing to perform the error correction on the target data again; and responsive to the performing of the error correction on the target data being successful, determining the first data as the error-corrected target data.

公开(公告)号：US12105588B2

公开(公告)日：2024-10-01

申请号：US17804483

申请日：2022-05-27

申请人： Pure Storage, Inc.

发明人： Yogesh R. Vedpathak ,  Ramin Rouzbeh ,  Jason K. Resch

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F21/10 ,  G06F21/44 ,  G06F21/60 ,  G06F21/62 ,  G06F21/64 ,  G06F21/80 ,  H03M13/00 ,  H03M13/29 ,  H03M13/37 ,  H04L9/00 ,  H04L9/08 ,  H04L9/32 ,  H04L67/10 ,  H04L67/1097 ,  H04L67/306 ,  H04L67/50 ,  H04L67/52 ,  H04L67/60 ,  G06F11/07 ,  H03M13/15

CPC分类号： G06F11/1076 ,  G06F11/1044 ,  G06F11/1092 ,  G06F11/142 ,  G06F11/2094 ,  G06F21/10 ,  G06F21/44 ,  G06F21/60 ,  G06F21/602 ,  G06F21/6218 ,  G06F21/6272 ,  G06F21/645 ,  G06F21/805 ,  H03M13/2909 ,  H03M13/3761 ,  H03M13/611 ,  H04L9/006 ,  H04L9/0841 ,  H04L9/085 ,  H04L9/0861 ,  H04L9/0894 ,  H04L9/3271 ,  H04L67/10 ,  H04L67/1097 ,  H04L67/306 ,  H04L67/52 ,  H04L67/535 ,  H04L67/60 ,  G06F11/0712 ,  G06F11/0784 ,  G06F11/0787 ,  G06F11/1004 ,  H03M13/1515 ,  H03M13/616 ,  H04L2209/34

摘要： A method includes writing sets of encoded data slices to storage units of a storage network in accordance with error encoding parameters, where for a set of encoded data slices, the error encoding parameters include an error coding number and a decode threshold number, the error coding number indicates a number of encoded data slices that results when a data segment is encoded using an error encoding function and the decode threshold number indicates a minimum number needed to recover the data segment. The method further includes monitoring processing of the writing the sets of encoded data slices to produce write processing performance information. When the write processing performance information compares unfavorably to a desired write performance range, the method further includes adjusting at least one of the error coding number and the decode threshold number to produce adjusted error encoding parameters for writing subsequent encoded data slices.

公开(公告)号：US20240322842A1

公开(公告)日：2024-09-26

申请号：US18735554

申请日：2024-06-06

申请人： Electronics and Telecommunications Research Institute

发明人： Sung-Ik PARK ,  Sun-Hyoung KWON ,  Jae-Young LEE ,  Heung-Mook KIM

IPC分类号： H03M13/15 ,  H03M13/00 ,  H03M13/11 ,  H03M13/25 ,  H03M13/27 ,  H03M13/29

CPC分类号： H03M13/152 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1165 ,  H03M13/271 ,  H03M13/2778 ,  H03M13/618 ,  H03M13/6362 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/6393 ,  H03M13/6552

摘要： A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

公开(公告)号：US20240313890A1

公开(公告)日：2024-09-19

申请号：US18669271

申请日：2024-05-20

申请人： QUALCOMM Incorporated

发明人： Ahmed Attia ABOTABL ,  Ahmed ELSHAFIE ,  Marwen ZORGUI ,  Ahmed Abdelaziz Ibrahim Abdelaziz ZEWAIL ,  Wanshi CHEN

IPC分类号： H04L1/00 ,  H03M13/00 ,  H03M13/11

CPC分类号： H04L1/0061 ,  H03M13/1111 ,  H03M13/611 ,  H04L1/0067

摘要： Methods, systems, and devices for wireless communication are described. A device may perform rate splitting on a first message for a first user equipment (UE) and a second message for a second UE, the first message comprising a first private portion and a first common portion, and the second message comprising a second private portion and a second common portion. The device may combine the first common portion and the second common portion into a third common portion. The device may generate cyclic redundancy check (CRC) parity bits associated with at least one of the first private portion and the third common portion and attach the generated CRC parity bits to one or more blocks associated with the transmission. The device may transmit the first private portion and the third common portion to the first UE, and the second private portion and the third common portion to the second UE.