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    NULL CONVENTION SPEED INDEPENDENT LOGIC
    1.
    发明申请
    NULL CONVENTION SPEED INDEPENDENT LOGIC 审中-公开
    NULL公约速度独立逻辑

    公开(公告)号：WO1992021083A1

    公开(公告)日：1992-11-26

    申请号：PCT/US1992004132

    申请日：1992-05-15

    Applicant: THESEUS RESEARCH INC.

    Inventor： THESEUS RESEARCH INC. ,  FANT, Karl, M. ,  BRANDT, Scott, A.

    IPC: G06F01/00

    CPC classification number: G06F7/502 ,  G06F7/00 ,  G06F7/5052 ,  G06F11/085 ,  G06F2207/4822 ,  H03K19/0813 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16

    Abstract: An information processing system comprising at least one information processing unit (A, B). The information processing unit has at least one information processing member which resolves allowed values. Allowed values include at least one data value and at least one non-data value. At least one non-data value is a null value. The system further comprises a plurality of information transmission elements (OA, NA) for transmitting values to and from the information processing unit (A) and the information processing member.

    Abstract translation: 一种信息处理系统，包括至少一个信息处理单元（A，B）。 信息处理单元具有至少一个解决允许值的信息处理部件。 允许的值包括至少一个数据值和至少一个非数据值。 至少一个非数据值是空值。 该系统还包括用于向信息处理单元（A）和信息处理单元（A）发送值的多个信息传输元件（OA，NA）。

    RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS
    2.
    发明申请
    RECONFIGURABLE LOGIC CELL MADE UP OF DOUBLE-GATE MOSFET TRANSISTORS 审中-公开
    可重构逻辑单元制造双栅MOSFET晶体管

    公开(公告)号：WO2009013422A3

    公开(公告)日：2009-03-12

    申请号：PCT/FR2008051309

    申请日：2008-07-11

    Applicant: LYON ECOLE CENTRALE ,  CENTRE NAT RECH SCIENT ,  O'CONNOR IAN D ,  HASSOUNE ILHAM

    Inventor： O'CONNOR IAN D ,  HASSOUNE ILHAM

    IPC: H03K19/08 ,  H03K19/0944 ,  H03K19/173

    CPC classification number: H03K19/09441 ,  H03K19/0813 ,  H03K19/1738

    Abstract: The invention relates to reconfigurable logic cells made up of double-gate MOSFET transistors (DG MOSFET) comprising n inputs (A,B), n being greater than or equal to 2, which can carry out at least four logical functions permitting the processing of the logical signals provided at the n inputs (A,B). According to the invention, the cell comprises at least one first branch between the earth and the cell output (F) with n MOSFET transistors (M1,M2) of the N type with a double gate in series and n-1 branches in parallel with the first branch, each provided with a MOSFET transistor (M3) of the N type with a double gate, each of the logical functions corresponding to a given configuration of the cell where a specific set of control signals (C1,C2) is applied to the back gate of at least some of the transistors (M2,M3), each control signal (C1,C2) placing the transistor (M2,M3) in a particular operating mode, the n inputs (A,B) being each connected to the front gate of one of the n transistors (M1,M2) of the first branch, n-1 inputs (B) also being connected to the front gate of one (M3) of the n-1 transistors of the n-1 branches parallel to the first branch.

    Abstract translation: 本发明涉及由包括n个输入（A，B），n大于或等于2的双栅极MOSFET晶体管（DG MOSFET）组成的可重构逻辑单元，其可以执行至少四个允许处理 在n个输入端提供的逻辑信号（A，B）。 根据本发明，电池包括地球和电池单元输出（F）之间的至少一个第一分支，其中N型的n型MOSFET晶体管（M1，M2）具有串联的双栅极，并且n-1个分支与 第一分支，每个具有带有双栅极的N型MOSFET晶体管（M3），每个逻辑功能对应于单元的给定配置，其中一组特定的控制信号（C1，C2）被施加到 至少一些晶体管（M2，M3）的背栅极，将晶体管（M2，M3）放置在特定工作模式中的每个控制信号（C1，C2），n个输入端（A，B）各自连接到 第一分支的n个晶体管（M1，M2）之一的前栅极，n-1个输入（B）也连接到n-1个分支的n-1个晶体管中的一个（M3）的前栅极 平行于第一分支。

    CIRCUIT FOR PRODUCING LOGIC ELEMENTS REPRESENTABLE BY THRESHOLD EQUATIONS
    4.
    发明申请
    CIRCUIT FOR PRODUCING LOGIC ELEMENTS REPRESENTABLE BY THRESHOLD EQUATIONS 审中-公开
    电路用于实现阈值方程的显示逻辑单元

    公开(公告)号：WO1996042048A1

    公开(公告)日：1996-12-27

    申请号：PCT/DE1996000981

    申请日：1996-06-04

    Applicant: SIEMENS AKTIENGESELLSCHAFT ,  PRANGE, Stefan ,  THEWES, Roland ,  WOHLRAB, Erdmute ,  WEBER, Werner

    Inventor： SIEMENS AKTIENGESELLSCHAFT

    IPC: G06F07/50

    CPC classification number: G06F7/5013 ,  G06F7/523 ,  G06F2207/4818 ,  H03K19/0813

    Abstract: The invention relates to a circuit by means of which all logic elements which can be represented in the form of a threshold equation can be produced. To this end, parallel transistors (T1, T2, T3, ..., Tn) of a transistor unit are dimensioned so that the transverse currents (It1, It2, It3, ..., Itn) flowing through the transistors (T1, T2, T3, ..., Tn) represents a weighted summand of a first term of the threshold equation. A second term in the threshold equation is formed by a reference current IR representing the value of the second term. An evaluation unit (BE) compares a total current found from the sum of the transverse currents (It1, It2, It3, ..., Itn with the reference current IR. The result of evaluation is provided in the form of a stable output signal at an output of the evaluation unit (BE).

    Abstract translation: 本发明涉及一种与可在阈值方程的形式来表示的所有逻辑元件可实现的电路布置。 为了这个目的，并联连接的晶体管（T1，T2，T3，...，TN）的尺寸使得一个晶体管单元（TE）的通过所述晶体管（T1，T2，T3，...，TN）流动的交叉电流（IT1 各自表示It2中，IT3，...，ITN）的阈值等式的第一项的加权被加数。 阈值方程的第二项是由所述第二术语参考电流IR的值的代表形成。 评估单元（BE）的总电流从横向电流（IT1，It2中，IT3，...，ITN）的结果的总和进行比较，与基准电流IR。 评价结果在一个稳定的输出信号的形式在所述评估单元（BE）的输出而获得。

    VOTING CIRCUITS AND METHODS FOR TRUSTED FAULT TOLERANCE OF A SYSTEM OF UNTRUSTED SUBSYSTEMS
    5.
    发明申请
    VOTING CIRCUITS AND METHODS FOR TRUSTED FAULT TOLERANCE OF A SYSTEM OF UNTRUSTED SUBSYSTEMS 审中-公开
    不确定子系统的可信容错问题的投票电路和方法

    公开(公告)号：WO2018048720A1

    公开(公告)日：2018-03-15

    申请号：PCT/US2017/049648

    申请日：2017-08-31

    Applicant: THE CHARLES STARK DRAPER LABORATORY, INC.

    Inventor： VIGEANT, Richard, L. ,  DE LA SERNA, Antonio, E.

    IPC: H03K19/23

    CPC classification number: H03K19/23 ,  G06F11/08 ,  G06F13/28 ,  G06F13/32 ,  G06F21/57 ,  G06F21/71 ,  G06F2211/1097 ,  G07C13/02 ,  H03K19/0813 ,  H03K25/02

    Abstract: Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.

    Abstract translation: 用于确定来自多个输入的多数投票的电路和方法。 示例电路包括投票输入阶段，传输阶段和累积阶段。 表决输入级包括至少三个输入开关电容器。 传输级包括对应于输入开关电容器的传输开关电容器。 在时钟信号的状态期间，转换开关电容器对与每个输入开关电容器对应的表决电容器充电。 累加级包括累加串联连接表决电容器的开关电容器。 累积的开关电容器使得表决电容器的电荷在时钟信号的交替状态期间累积。 表决电容器的累积电荷表示输入开关电容器的大部分投票。

    THRESHOLD LOGIC WITH IMPROVED SIGNAL-TO-NOISE RATIO
    7.
    发明申请
    THRESHOLD LOGIC WITH IMPROVED SIGNAL-TO-NOISE RATIO 审中-公开
    具有改进的信噪比的阈值逻辑

    公开(公告)号：WO1997033372A1

    公开(公告)日：1997-09-12

    申请号：PCT/DE1997000355

    申请日：1997-02-27

    Applicant: SIEMENS AKTIENGESELLSCHAFT ,  WEBER, Werner ,  THEWES, Roland ,  LUCK, Andreas

    Inventor： SIEMENS AKTIENGESELLSCHAFT

    IPC: H03K19/0944

    CPC classification number: G06F7/53 ,  G06F2207/4826 ,  H03K19/0027 ,  H03K19/0813

    Abstract: The subject of the application concerns threshold logic in which a non-inverting circuit branch (S) and an inverting circuit branch (S') are connected with at least one comparative weighting circuit (BC, BS), where the non-inverting circuit branch and the inverting circuit branch preferably are constructed alike and, in each case, contain at least one neuron transistor (NT1, NT1'), and where the corresponding neuron transistor gates in the non-inverting and the inverting circuit branches are activated inversely to one another.

    Abstract translation: 本申请的主题涉及一种阈值的逻辑，其中，一个非反相电路分支（S）和反相电路分支（S“）与至少一个比较点评局部电路（BC，BS）被连接时，其中该非反相电路分支和反相电路分支优选地是相同的结构，并且分别具有至少 一个神经晶体管（NT1 NT1“）和包含相应的神经晶体管栅极中的非反相和在电路分支彼此反相成反比驱动。

    一种非易失性布尔逻辑运算电路及其操作方法
    8.
    发明申请
    一种非易失性布尔逻辑运算电路及其操作方法 审中-公开

    公开(公告)号：WO2015192414A1

    公开(公告)日：2015-12-23

    申请号：PCT/CN2014/081870

    申请日：2014-07-09

    Applicant: 华中科技大学

    Inventor： 缪向水 ,  周亚雄 ,  李祎 ,  孙华军

    IPC: H03K19/173

    CPC classification number: H03K19/0002 ,  H03K19/0021 ,  H03K19/0813 ,  H03K19/20

    Abstract: 一种非易失性布尔逻辑运算电路及其操作方法，布尔逻辑运算电路具有两个输入端（A，B）和一个输出端（C），包括第一阻变元件（M 1 ）和第二阻变元件（M 2 ）；第一阻变元件（M 1 ）的负极（511）作为逻辑运算电路的第一输入端（A），第二阻变元件（M 2 ）的负极（521）作为逻辑运算电路的第二输入端（B），第二阻变元件（M 2 ）的正极（522）与第一阻变元件（M 1 ）的正极（512）连接后作为逻辑运算电路的输出端（C）。通过对非易失性布尔逻辑运算电路进行操作可实现至少16种基本布尔逻辑操作。通过两个阻变元件（M 1 ，M 2 ）搭建的逻辑电路，可根据需求实现至少16种基本布尔逻辑运算，逻辑运算的结果直接存储在阻变元件（M 1 ，M 2 ）的电阻状态中，实现了计算和存储的融合，并且逻辑电路所需的器件数少、操作简单，因此，可以节省计算功耗和时间，提高计算效率。

    THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE
    9.
    发明申请
    THRESHOLD LOGIC ELEMENT HAVING LOW LEAKAGE POWER AND HIGH PERFORMANCE 审中-公开
    THRESHOLD逻辑元件具有低漏电和高性能

    公开(公告)号：WO2009102948A3

    公开(公告)日：2009-10-08

    申请号：PCT/US2009034044

    申请日：2009-02-13

    Applicant: UNIV ARIZONA STATE ,  LESHNER SAMUEL ,  VRUDHULA SARMA

    Inventor： LESHNER SAMUEL ,  VRUDHULA SARMA

    IPC: H03K19/08 ,  G06F7/02 ,  G06N3/063

    CPC classification number: H03K19/0813

    Abstract: Embodiments of a threshold logic element are provided. Preferably, embodiments of the threshold logic element discussed herein have low leakage power and high performance characteristics. In the preferred embodiment, the threshold logic element is a threshold logic latch (TLL). The TLL is a dynamically operated current-mode threshold logic cell that provides fast and efficient implementation of digital logic functions. The TLL can be operated synchronously or asynchronously and is fully compatible with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology.

    Abstract translation: 提供阈值逻辑元件的实施例。 优选地，本文讨论的阈值逻辑元件的实施例具有低泄漏功率和高性能特性。 在优选实施例中，阈值逻辑元件是阈值逻辑锁存器（TLL）。 TLL是一种动态操作的电流模式阈值逻辑单元，可快速有效地实现数字逻辑功能。 TLL可以同步或异步操作，并与标准互补金属氧化物半导体（CMOS）技术完全兼容。

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