公开(公告)号：WO2004066373A1

公开(公告)日：2004-08-05

申请号：PCT/EP2003/014751

申请日：2003-12-22

Applicant: AUSTRIAMICROSYSTEMS AG ,  KNAIPP, Martin

Inventor： KNAIPP, Martin

IPC: H01L21/225

CPC classification number: H01L21/266 ,  H01L21/2253

Abstract: Es wird vorgeschlagen, zur Herstellung eines definierten Dotierungsgebietes (DG) den Dotierstoff über eine Maske (M,MO) in das Halbleitermaterial (S) zu implantieren und anschliessend unter definierten Eintreibbedingungen in eine gewünschte Tiefe einzudiffundieren. Zum Erzeugen eines gleichmässigen Dotierstoffprofils wird bei der Implantation eine Maske (M,MO) verwendet, die eine ringförmig geschlossene, für den Dotierstoff durchlässige Maskenöffnung (MO) aufweist, die einen für Dotierstoff undurchlässigen Maskenbereich (MZ) umgibt.

Abstract translation: 它提出了一种用于产生定义掺杂区域（DG）通过在半导体材料（S）的掩模（M，MO）到注入掺杂剂并扩散到期望的深度在驱动条件下定义的。 用于产生在一个掩模（M，MO）的注入均匀的掺杂剂分布时，具有环形封闭的，可渗透的掺杂剂掩模开口（MO），其包围的掺杂剂不可渗透的掩模区域（MZ）。

公开(公告)号：WO03005452A3

公开(公告)日：2003-09-04

申请号：PCT/US0220301

申请日：2002-06-21

Applicant: SILICONIX INC

Inventor： DARWISH MOHAMED N

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/2253 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7813

Abstract: A trench MOSFET (30) is formed in a structure which includes a P-type epitaxial layer (34) overlying an N+ substrate (32). An N-type dopant is implanted through the bottom of the trench (35) into the P-epitaxial layer to form a buried layer below the trench, and after a up-diffusion step a N drain-drift region (33) extends between the N+ substrate and the bottom of the trench. The result is a more controllable doping profile of the N-type dopant below the trench. The body region (34A) may also be formed by implanting P-type dopant into the epitaxial layer, in which case the background doping of the epitaxial layer may be either lightly doped P- or N-type. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract translation: 沟槽MOSFET（30）形成为包括覆盖在N +衬底（32）上的P型外延层（34）的结构。 通过沟槽（35）的底部将N型掺杂剂注入到P外延层中以在沟槽下形成掩埋层，并且在上扩散步骤之后，N漏极漂移区域（33）在 N +衬底和沟槽的底部。 结果是沟槽下方的N型掺杂剂的更可控的掺杂分布。 也可以通过将P型掺杂剂注入到外延层中来形成体区（34A），在这种情况下，外延层的背景掺杂可以是轻掺杂的P型或N型。 根据本发明构造的MOSFET可以具有降低的阈值电压和导通电阻以及增加的穿通击穿电压。

公开(公告)号：WO0008691A9

公开(公告)日：2002-01-31

申请号：PCT/US9917486

申请日：1999-08-02

Applicant: UNIV MISSOURI

Inventor： WHITE HENRY W ,  ZHU SHEN ,  RYU YUNGRYEL

IPC: H01L29/22 ,  C23C14/08 ,  C23C14/28 ,  C30B23/02 ,  H01L21/203 ,  H01L21/22 ,  H01L21/225 ,  H01L21/363 ,  H01L21/385 ,  H01L31/0296 ,  H01L31/10 ,  H01L31/18 ,  H01L33/00 ,  H01L33/28 ,  H01S5/327

CPC classification number: H01L33/285 ,  C23C14/081 ,  C23C14/086 ,  C23C14/28 ,  C30B23/02 ,  C30B29/16 ,  H01L21/0237 ,  H01L21/02395 ,  H01L21/02472 ,  H01L21/02554 ,  H01L21/0256 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02631 ,  H01L21/02661 ,  H01L21/2225 ,  H01L21/2255 ,  H01L31/02963 ,  H01L31/1836 ,  H01L33/0087 ,  Y02E10/50 ,  Y10S148/113 ,  Y10T428/12681

Abstract: A p-type zinc oxide film and a process for preparing the film and p-n or n-p junctions is disclosed. In a preferred embodiment, the p-type zinc oxide film contains arsenic and is grown on a gallium arsenide substrate. The p-type zinc oxide film has a net acceptor concentration of at least about 10 acceptors/cm , a resistivity of no greater than about 1 ohm-cm, and a Hall mobility of between about 0.1 and about 50 cm /Vs.

Abstract translation: 公开了一种p型氧化锌膜和制备该膜和p-n或n-p结的方法。 在优选的实施方案中，p型氧化锌膜含有砷并在砷化镓衬底上生长。 p型氧化锌膜具有至少约10 15个受体/ cm 3的净受主浓度，不大于约1欧姆 - 厘米的电阻率和约0.1至约50的霍尔迁移率 厘米<2> / Vs以上。

公开(公告)号：WO01095398A1

公开(公告)日：2001-12-13

申请号：PCT/US2001/017745

申请日：2001-06-01

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66712

Abstract: A power MOSFET is provided that includes a substrate (2) of a first conductivity type. An epitaxial layer (1) also of the first conductivity type is deposited on the substrate. First and second body regions (5a, 6a, 5b, 6b) are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions (7, 8) of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches (44, 46) are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches so as to form semiconductor regions (40, 42) of the second conductivity type under the body regions.

Abstract translation: 提供功率MOSFET，其包括第一导电类型的衬底（2）。 在衬底上沉积也具有第一导电类型的外延层（1）。 第一和第二体区（5a，6a，5b，6b）位于外延层中并在它们之间限定漂移区。 身体区域具有第二导电类型。 第一导电类型的第一和第二源极区域（7,8）分别位于第一和第二体区域中。 多个沟槽（44,46）位于外延层的漂移区域的主体区域的下方。 从第一和第二体区向衬底延伸的沟槽填充有包含第二导电类型的掺杂剂的外延层状材料。 掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分，以便在体区域下形成第二导电类型的半导体区域（40,42）。

公开(公告)号：WO01073828A1

公开(公告)日：2001-10-04

申请号：PCT/US2001/009200

申请日：2001-03-22

IPC: H01L21/22 ,  C30B33/00 ,  H01L21/225 ,  H01L21/38

CPC classification number: H01L21/2255 ,  C30B29/06 ,  C30B31/02 ,  C30B33/005 ,  H01L21/2225 ,  H01L21/223

Abstract: A method of doping silicon that involves placing a silicon wafer in spaced relationship to a solid phosphorus dopant source at a first temperature for a time sufficient to deposit a phosphorus-containing layer on the surface of the wafer and subsequently oxidizing the doped silicon wafer with wet oxygen or pyrogenic steam at a second temperature lower than the first temperature. The silicon wafer is maintained in spaced relationship to the solid phosphorus dopant source during the oxidizing step. The temperatures are selected such that the solid phosphorus dopant source evolves P>2 5 2 5

Abstract translation: 一种掺杂硅的方法，其涉及将硅晶片在第一温度下与固态磷掺杂剂源间隔开的时间足以将含磷层沉积在晶片的表面上，随后用湿法氧化掺杂的硅晶片 氧气或热原蒸汽在低于第一温度的第二温度下进行。 在氧化步骤期间，硅晶片保持与固体磷掺杂剂源的间隔关系。 选择温度使得固体磷掺杂剂源在第一温度下放出P> 2℃，第二温度足够低于第一温度以降低从固体产生的P> 2 <5的演化 磷掺杂剂源。

公开(公告)号：WO01052313A1

公开(公告)日：2001-07-19

申请号：PCT/EP2000/013221

申请日：2000-12-27

IPC: H01L21/22 ,  H01L21/20 ,  H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/66757 ,  H01L29/4908 ,  H01L29/78618

Abstract: A method of producing a top gate thin-film transistor in which an insulated gate structure (14) is formed over an amorphous silicon layer with upper gate conductor (16) directly over the gate insulator layers. The gate conductor is patterned to be narrower than a spacing to be provided between source and drain electrode contacts. Laser annealing of areas of the amorphous silicon layer (12) not shielded by the gate conductor (16) is carried out to form polysilicon portions. The gate insulator layers are formed as a gate insulator layer (14a,14b) of first refractive index, and an overlying surface insulator layer (14c) of second, lower, refractive index. The overlying surface insulator layer has been found to reduce fluctuations in the reflectance of the structure in dependence upon the specific thicknesses of the gate insulator layers. Therefore, the tolerances for the thicknesses of the gate insulator layers can be reduced whilst maintaining control of the laser annealing process.

Abstract translation: 一种制造顶栅极薄膜晶体管的方法，其中绝缘栅极结构（14）形成在非晶硅层上，上层栅极导体（16）直接位于栅极绝缘体层上。 栅极导体被图案化成比在源极和漏极电极触点之间提供的间隔窄。 进行未被栅极导体（16）屏蔽的非晶硅层（12）的区域的激光退火，以形成多晶硅部分。 栅极绝缘体层形成为具有第一折射率的栅极绝缘体层（14a，14b）和第二，较低折射率的覆盖表面绝缘体层（14c）。 已经发现覆盖表面绝缘体层根据栅极绝缘体层的具体厚度减小结构的反射率的波动。 因此，可以减小栅极绝缘体层的厚度的公差，同时保持激光退火过程的控制。

公开(公告)号：WO01011668A1

公开(公告)日：2001-02-15

申请号：PCT/JP2000/005107

申请日：2000-07-28

IPC: H01L29/73 ,  H01L21/225 ,  H01L21/265 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/92 ,  H01L21/28 ,  H01L27/04 ,  H01L27/088 ,  H01L29/72

CPC classification number: H01L27/092 ,  H01L21/2254 ,  H01L21/823842

Abstract: A MOS transistor is manufactured. A eutectic semiconductor layer (4) of silicon and germanium is formed on a semiconductor substrate (10). The eutectic semiconductor layer (4) of silicon and germanium is doped at an impurity concentration greater than 10 /cm by ion implantation. The doped eutectic semiconductor layer is heat-treated to form a diffused layer (5) having a low resistance and a shallow junction by solid-phase diffusion from the eutectic semiconductor layer (4). The doped eutectic semiconductor layer (4) of silicon and germanium is then removed using an etching solution to form source and drain regions.

Abstract translation: 制造了MOS晶体管。 在半导体衬底（10）上形成硅和锗的共晶半导体层（4）。 硅和锗的共晶半导体层（4）通过离子注入以大于10 20 / cm 3的杂质浓度被掺杂。 掺杂的共晶半导体层通过从共晶半导体层（4）的固相扩散而被热处理以形成具有低电阻和浅结的扩散层（5）。 然后使用蚀刻溶液去除硅和锗的掺杂共晶半导体层（4），以形成源区和漏区。

公开(公告)号：WO0052738A3

公开(公告)日：2000-12-21

申请号：PCT/DE0000546

申请日：2000-02-25

Applicant: BOSCH GMBH ROBERT ,  SPITZ RICHARD ,  GOERLACH ALFRED ,  WILL BARBARA ,  UEBBING HELGA ,  RIEKERT ROLAND ,  ADAMSKI CHRISTIAN

Inventor： SPITZ RICHARD ,  GOERLACH ALFRED ,  WILL BARBARA ,  UEBBING HELGA ,  RIEKERT ROLAND ,  ADAMSKI CHRISTIAN

IPC: H01L21/225 ,  H01L21/329

CPC classification number: H01L29/66136 ,  H01L21/2255

Abstract: The invention relates to a method for producing semiconductor components. At least one highly doped area is introduced into a wafer. A solid glass layer (2; 4; 2, 3; 4, 5) which is provided with a doping agent is mounted on at least one of the two sides of a semiconductor wafer (1). In a further step, the wafer is heated to high temperatures in such a way that the doping agent leaves the glass layer and penetrates deep into the wafer in order to produce the at least one doped area (10; 11). In a further step, the glass layer is removed. The inventive method is used for producing homogeneous, highly doped areas. Said areas can be introduced through the two sides of the wafer and can have different doping types.

Abstract translation: 本发明涉及一种用于制造半导体部件的方法，其中至少一个掺杂区被引入到晶片中，其中在半导体晶片（1）的两侧中的至少一侧上形成设置有掺杂剂的固体玻璃层（2,4,2,3,4） ，5），在另一步骤中，晶片被加热到高温，使得来自玻璃层的掺杂剂深入到晶片中以产生至少一个掺杂区域（10,11），并且在进一步的步骤中，玻璃层 被删除。 该方法用于产生均匀的高掺杂区域，其中这些区域也可以在晶片的两侧引入并且可以具有不同的掺杂类型。

公开(公告)号：WO0033386A3

公开(公告)日：2000-11-16

申请号：PCT/EP9908951

申请日：1999-11-16

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HURKX GODEFRIDUS A M ,  HUETING RAYMOND J E

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/2255 ,  H01L29/42368 ,  H01L29/7813

Abstract: In a trench-gate semiconductor device, for example a cellular power MOSFET, the gate (11) is present in a trench (20) that extends through the channel-accommodating region (15) of the device. An underlying body portion (16) that carries a high voltage in an off state of the device is present adjacent to a side wall of a lower part (20b) of the trench (20). Instead of being a single high-resistivity region, this body portion (16) comprises first regions (61) of a first conductivity type interposed with second regions (62) of the opposite second conductivity type. In the conducting state of the device, the first regions (61) provide parallel current paths through the thick body portion (16), from the conduction channel (12) in the channel-accommodating region (15). In an off-state of the device, the body portion (16) carries a depletion layer (50). The first region (61) of this body portion (16) is present between the second region (62) and the side wall (22) of the lower part (20b) of the trench (20) and has a doping concentration (Nd) of the first conductivity type that is higher than the doping concentration (Na) of the second conductivity type of the second region (62). A balanced space charge is nonetheless obtained by depletion of the first and second regions (61, 62), because the width (W1) of the first region (61) is made smaller than the width (W2) of the lower-doped second region (62). This device structure can have a low on-resistance and high breakdown voltage, while also permitting its commercial manufacture using dopant out-diffusion from the lower trench part (20b) into the lower-doped second region (62) to form the first region (61).

Abstract translation: 在沟槽栅极半导体器件（例如蜂窝功率MOSFET）中，栅极（11）存在于延伸穿过器件的沟道容纳区域（15）的沟槽（20）中。 在器件的断开状态下承载高电压的下部主体部分（16）与沟槽（20）的下部（20b）的侧壁相邻。 代替单个高电阻率区域，该主体部分（16）包括插入与相对的第二导电类型的第二区域（62）的第一导电类型的第一区域（61）。 在器件的导通状态下，第一区域（61）从通道容纳区域（15）中的导电通道（12）提供穿过厚体部分（16）的平行电流路径。 在装置的关闭状态下，主体部分（16）承载耗尽层（50）。 本体部分（16）的第一区域（61）存在于沟槽（20）的下部（20b）的第二区域（62）和侧壁（22）之间，并具有掺杂浓度（Nd） 的第一导电类型，其高于第二区域（62）的第二导电类型的掺杂浓度（Na）。 然而，由于使第一区域（61）的宽度（W1）小于下掺杂第二区域（61）的宽度（W2），因此第一和第二区域（61,62）的耗尽可以获得均衡的空间电荷 （62）。 该器件结构可以具有低的导通电阻和高的击穿电压，同时还允许使用从下沟槽部分（20b）向下掺杂的第二区域（62）的掺杂剂扩散的商业制造以形成第一区域 61）。

公开(公告)号：WO0013227A3

公开(公告)日：2000-06-02

申请号：PCT/EP9905600

申请日：1999-08-03

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： EMONS CATHARINA H H ,  TERPSTRA DOEDE ,  TIMMERING CORNELIS E ,  DE BOER WIEBE B

IPC: H01L21/22 ,  H01L21/223 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/223 ,  H01L21/2252 ,  H01L29/66242

Abstract: The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950 DEG C for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850 DEG C.

Abstract translation: 本发明涉及一种制造离散或集成双极晶体管的方法，其包括基极（1A），发射极（2）和集电极（3）。 通过为半导体本体（10）提供半导体本体（1）的单晶部分（3）上的掺杂半导体层（1）来形成基极（1A）的基极（1A）和连接区域（1B） 其形成收集器（3）。 在所述基底之外，层（1）与半导体本体（10）的非单晶部分（4）相接合，并形成基底（1A）的非单晶连接区域（1B）。 通过掩模（5），选择性地增加掩模（5）外的层（1）的掺杂浓度，导致高导电连接区域（1B）和非常快的晶体管。 在已知的方法中，为此目的使用离子注入。 在根据本发明的方法中，这是通过使半导体本体（10）与包括掺杂元素的气态物质（40）接触并且以这样的方式加热半导体本体（10）来实现的，即掺杂元件 渗透到半导体层（1）中。 气态物质（40）例如乙硼烷的供应优选在800-950℃的温度下进行1至数分钟。 随后，稍长的扩散步骤可以在例如850℃下进行。