公开(公告)号：WO2018209200A2

公开(公告)日：2018-11-15

申请号：PCT/US2018/032267

申请日：2018-05-11

Applicant: APPLIED MATERIALS, INC.

Inventor： KULSHRESHTHA, Prashant Kumar ,  WANG, Jiarui ,  LEE, Kwangduk Douglas ,  GADRE, Milind ,  MIN, Xiaoquan ,  CONNORS, Paul

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/2257 ,  C23C16/24 ,  C23C16/42 ,  C23C16/45538 ,  G03F1/38 ,  H01L21/0332 ,  H01L21/32053 ,  H01L21/76876

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

公开(公告)号：WO2015050776A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/057577

申请日：2014-09-26

Applicant: VISHAY GENERAL SEMICONDUCTOR LLC

Inventor： CHEN, Shih-Kuan ,  CHIANG, Wan-Lan ,  LIN, Yih-Yin ,  CHIANG, Ming-Tai ,  PENG, Chih-Ping

IPC: H01L29/866

CPC classification number: H01L29/0611 ,  H01L21/2253 ,  H01L21/2257 ,  H01L21/2652 ,  H01L21/283 ,  H01L29/456 ,  H01L29/66106 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/866

Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.

Abstract translation: 诸如齐纳二极管的半导体器件包括第一导电类型的第一半导体材料和与第一半导体材料接触形成第二导电类型的第二导电类型的第二半导体材料，以形成它们之间的连接点。 第一氧化物层设置在第二半导体材料的一部分上，使得第二半导体材料的剩余部分被暴露。 多晶硅层设置在第二半导体材料的暴露部分和第一氧化物层的一部分上。 第一导电层设置在多晶硅层上。 第二导电层设置在与第二半导体材料接触的与第一半导体材料的表面相对的第一半导体材料的表面上。

公开(公告)号：WO02065516A8

公开(公告)日：2004-07-08

申请号：PCT/US0204746

申请日：2002-02-12

Applicant: ASM INC

Inventor： TODD MICHAEL A

IPC: C23C16/24 ,  C23C16/02 ,  C23C16/42 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/331 ,  H01L21/337 ,  H01L21/425 ,  H01L21/469 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/51 ,  H01L29/737 ,  H01L29/78 ,  H01L31/18 ,  H01L31/20 ,  C23C16/00

CPC classification number: C23C16/0272 ,  B82Y10/00 ,  B82Y30/00 ,  C23C16/22 ,  C23C16/24 ,  C23C16/30 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/56 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3185 ,  H01L21/32055 ,  H01L28/84 ,  H01L29/127 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66242 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

Abstract: Chemical vapor deposition processes utilize higher order silanes and germanium precursors as chemical precursors. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, trisilane is employed to deposit SiGe-containing films that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract translation: 化学气相沉积工艺利用高阶硅烷和锗前体作为化学前体。 这些方法具有高的沉积速率，但是与使用常规化学前体制备的膜相比，在组成和厚度方面产生更均匀的膜。 在优选的实施方案中，使用丙硅烷沉积在诸如晶体管栅电极的各种应用中可用于半导体工业中的含SiGe的膜。

公开(公告)号：WO2002064853A2

公开(公告)日：2002-08-22

申请号：PCT/US2002/004751

申请日：2002-02-12

Applicant: ASM AMERICA, INC.

Inventor： TODD, Michael, A. ,  RAAIJMAKERS, Ivo

IPC: C23C16/00

CPC classification number: C23C16/0272 ,  B82Y10/00 ,  B82Y30/00 ,  C23C16/22 ,  C23C16/24 ,  C23C16/30 ,  C23C16/308 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/56 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/2257 ,  H01L21/28035 ,  H01L21/28044 ,  H01L21/28194 ,  H01L21/28525 ,  H01L21/28556 ,  H01L21/3185 ,  H01L21/32055 ,  H01L28/84 ,  H01L29/127 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/66242 ,  H01L31/1804 ,  H01L31/182 ,  H01L31/202 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

Abstract: Thin, smooth silicon-containing films are prepared by deposition methods that utilize trisilane as a silicon source. In preferred embodiments, the methods result in Si-containing films that are continuous and have a thickness of about 150 Å or less, a surface roughness of about 5 Å rms or less, and a thickness non-uniformity of about 20% or less. Preferred silicon-containing films display a high degree of compositional uniformity when doped or alloyed with other elements. Preferred deposition methods provide improved manufacturing efficiency and can be used to make various useful structures such as wetting layers, HSG silicon, quantum dots, dielectric layers, anti-reflective coatings (ARC's), gate electrodes and diffusion sources.

Abstract translation: 通过使用丙硅烷作为硅源的沉积方法制备薄的平滑的含硅膜。 在优选的实施方案中，该方法产生连续的并且具有约150或更小的厚度，大约5范围或更小的表面粗糙度和约20％或更小的厚度不均匀性的含Si薄膜。 当与其它元素掺杂或合金化时，优选的含硅膜显示出高度的组成均匀性。 优选的沉积方法提供了改进的制造效率，并且可以用于制备各种有用的结构，例如润湿层，HSG硅，量子点，电介质层，抗反射涂层（ARC），栅电极和扩散源。

公开(公告)号：WO01095385A1

公开(公告)日：2001-12-13

申请号：PCT/US2001/018007

申请日：2001-06-01

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66712

Abstract: A method of making a high voltage MOSFET, wherein a substrate (2) of a first conductivity type is provided, an epitaxial layer (1) also of the first conductivity type is deposited on the substrate, a plurality of trenches (44, 46) are formed in the drift region of the epitaxial layer, the trenches, which extend toward the substrate from the first and second body regions (5a, 6a, 5b, 6b), are filled with a material that includes a dopant of the second conductivity type, and the dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. Furthermore, a breakdown voltage is measured in the epitaxial layer and compared to a desired breakdown voltage, an additional diffusion time being determined by using a predetermined relationship between diffusion time and breakdown voltage, and a further diffusionstep is perfomed for said additional diffusion time.

Abstract translation: 一种制造高压MOSFET的方法，其中提供第一导电类型的衬底（2），在衬底上沉积第一导电类型的外延层（1），多个沟槽（44,46） 形成在外延层的漂移区域中，从第一和第二体区（5a，6a，5b，6b）向衬底延伸的沟槽填充有包括第二导电类型的掺杂剂的材料 并且掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分。 此外，在外延层中测量击穿电压并与期望的击穿电压进行比较，通过使用扩散时间和击穿电压之间的预定关系来确定额外的扩散时间，并对所述额外的扩散时间进行进一步扩散步骤。

公开(公告)号：WO01033622A1

公开(公告)日：2001-05-10

申请号：PCT/US2000/029329

申请日：2000-10-24

IPC: H01L21/8247 ,  H01L21/225 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66825 ,  H01L21/2257

Abstract: A method of manufacturing a flash memory device in which minimal gate edge lifting is accomplished by minimally oxidizing the gate stack and exposed surface of the substrate, anisotropically etching the layer of oxide from the substrate, forming a doped solid source material on portions of the substrate in which source regions are to be formed and diffusing the dopants from the solid source material into the substrate.

Abstract translation: 一种制造闪速存储器件的方法，其中通过最小化氧化栅极堆叠和衬底的暴露表面来实现最小栅极边缘提升，从衬底各向异性地蚀刻氧化层，在衬底的部分上形成掺杂的固体源材料 其中将形成源区并将掺杂剂从固体源材料扩散到衬底中。

公开(公告)号：WO00075965A3

公开(公告)日：2001-05-03

申请号：PCT/US2000/015189

申请日：2000-06-02

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power MOSFET is provided that includes a substrate (2) of a first conductivity type. An epitaxial layer (1) also of the first conductivity type is deposited on the substrate. First and second body regions (5a, 6a, 5b, 6b) are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions (7, 8) of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches (44, 46) are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches so as to form semiconductor regions (40, 42) of the second conductivity type under the body regions.

Abstract translation: 提供功率MOSFET，其包括第一导电类型的衬底（2）。 在衬底上沉积也具有第一导电类型的外延层（1）。 第一和第二体区（5a，6a，5b，6b）位于外延层中并且在它们之间限定漂移区。 身体区域具有第二导电类型。 第一导电类型的第一和第二源极区域（7,8）分别位于第一和第二体区域中。 多个沟槽（44,46）位于外延层的漂移区域内的主体区域的下方。 从第一和第二体区向衬底延伸的沟槽填充有包括第二导电类型的掺杂剂的材料。 掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分，以便在体区域下形成第二导电类型的半导体区域（40,42）。

公开(公告)号：WO01003202A1

公开(公告)日：2001-01-11

申请号：PCT/JP2000/004224

申请日：2000-06-28

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/66712 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for producing a vertical semiconductor device having a structural part where n - semiconductor regions and p - semiconductor regions are alternated without burying in a trench by epitaxial growth. A p - silicon layer (13) to serve as a p - semiconductor regions (12) is formed. From the side wall of a first trench (22) formed in the p - silicon layer (13), n - type impurities are diffused into the p - silicon layer (13) to form a n - semiconductor region (11).

Abstract translation: 一种用于制造具有结构部分的垂直半导体器件的方法，其中n半导体区域和p半导体区域交替而不通过外延生长在沟槽中埋入。 形成用作p半导体区域（12）的p硅层（13）。 从p型硅层（13）中形成的第一沟槽（22）的侧壁，n型杂质扩散到p-硅层（13）中以形成n-半导体区域（11）。

公开(公告)号：WO0075965A2

公开(公告)日：2000-12-14

申请号：PCT/US0015189

申请日：2000-06-02

Applicant: GEN SEMICONDUCTOR INC

Inventor： BLANCHARD RICHARD A

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/66 ,  H01L29/06 ,  H01L29/78 ,  H01L

CPC classification number: H01L29/66712 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power MOSFET is provided that includes a substrate (2) of a first conductivity type. An epitaxial layer (1) also of the first conductivity type is deposited on the substrate. First and second body regions (5a, 6a, 5b, 6b) are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions (7, 8) of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches (44, 46) are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches so as to form semiconductor regions (40, 42) of the second conductivity type under the body regions.

Abstract translation: 提供功率MOSFET，其包括第一导电类型的衬底（2）。 在衬底上沉积也具有第一导电类型的外延层（1）。 第一和第二体区（5a，6a，5b，6b）位于外延层中并在它们之间限定漂移区。 身体区域具有第二导电类型。 第一导电类型的第一和第二源极区域（7,8）分别位于第一和第二体区域中。 多个沟槽（44,46）位于外延层的漂移区域的主体区域的下方。 从第一和第二体区向衬底延伸的沟槽填充有包括第二导电类型的掺杂剂的材料。 掺杂剂从沟槽扩散到与沟槽相邻的外延层的部分，以便在体区域下形成第二导电类型的半导体区域（40,42）。

公开(公告)号：WO1996041367A2

公开(公告)日：1996-12-19

申请号：PCT/IB1996000708

申请日：1996-06-03

Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

Inventor： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  WEINER, Kurt, H.

IPC: H01L00/00

CPC classification number: H01L29/6659 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/823814 ,  Y10S148/09 ,  Y10S438/923

Abstract: A doping sequence that reduces the cost and complexity of forming source/drain regions in complementary metal oxide silicon (CMOS) integrated circuit technologies. The process combines the use of patterned excimer laser annealing, dopant-saturated spin-on glass, silicide contact structures and interference effects created by thin dielectric layers to produce source and drain junctions that are ultrashallow in depth but exhibit low sheet and contact resistance. The process utilizes no photolithography and can be achieved without the use of expensive vacuum equipment. The process margins are wide, and yield loss due to contact of the ultrashallow dopants is eliminated.

Abstract translation: 一种掺杂顺序，降低了在互补金属氧化物硅（CMOS）集成电路技术中形成源极/漏极区域的成本和复杂性。 该方法结合了使用图案化准分子激光退火，掺杂剂饱和旋涂玻璃，硅化物接触结构和由薄介电层产生的干涉效应，以产生深度较小但具有低的片和接触电阻的源极和漏极结。 该方法不使用光刻并且可以在不使用昂贵的真空设备的情况下实现。 工艺裕度宽，消除了由于超低掺杂剂的接触导致的屈服损失。