公开(公告)号：WO03030360A3

公开(公告)日：2003-08-28

申请号：PCT/US0229443

申请日：2002-09-17

申请人： HONEYWELL INT INC

发明人： HYNES OWEN J

IPC分类号： H03K19/003 ,  H03K3/356 ,  H03K17/10

CPC分类号： H03K19/00315

摘要： A high-voltage output buffer is implemented in a low-voltage semiconductor process. The buffer comprises a level translator circuit, the level translator operable to receive a signal varying between ground and a low voltage level, and to output a corresponding signal varying between a reference voltage level and a high voltage level. The reference voltage level is an intermediate voltage level between half of the low voltage level and the high voltage level. The buffer further comprises an output circuit operable to receive via an input the output of the level translator circuit, and to output a high voltage level when the input is a high voltage level or a zero voltage level when the input is at the reference voltage level.

摘要翻译： 在低电压半导体工艺中实现高压输出缓冲器。 缓冲器包括电平转换器电路，电平转换器可操作以接收在接地和低电压电平之间变化的信号，并输出在参考电压电平和高电压电平之间变化的相应信号。 参考电压电平是低电平电平的一半和高电压电平之间的中间电压电平。 该缓冲器还包括输出电路，其可操作以经由输入端接收电平转换器电路的输出，并且当输入为参考电压电平时，当输入为高电压电平或零电压电平时输出高电压电平 。

公开(公告)号：WO02052726A1

公开(公告)日：2002-07-04

申请号：PCT/IB2000/001968

申请日：2000-12-27

IPC分类号： H03K17/30 ,  H03K17/10 ,  H03K17/12 ,  H03K17/687

CPC分类号： H03K17/127 ,  H03K17/10 ,  H03K17/107 ,  H03K17/12

摘要： A method for the dynamic load-balancing of series- and/or parallel-wired power semiconductor circuits (S1...S4) is disclosed. Individual switching signals (iG1, iG2) for the power semiconductor circuits (S1...S4) are generated, whereby a synchronous sampling timepoint (tsj) with system-wide validity is determined independently for each power semiconductor circuit (S1...S4) based on a synchronous event (es) in the whole circuit (1, 4). Error signals between actual values (ai), simultaneously measured at the sampling timepoint (tsj) and given set values (as) of an asynchronous state variable (a(t)) for the power semiconductor circuit (S1...S4), are reduced in the same or subsequent switching cycle. Alternatively, error signals between actual time values (tai) and set time values (tas) are minimised, whereby the set time values (tai) are measured on a global given threshold value ( epsilon a), for an asynchronous state variable (a(t)) for the power semiconductor circuit (S1...S4), being exceeded. Execution examples include: shifting the sampling timepoint (tsj) by a global set time interval ( DELTA t0), set value determination locally or globally, for example by means of averaging actual values (ai, tai), additional balancing of the gradients of asynchronous state variables (a(t)). Absence of a central sampling command, improves switching synchronisation, shortens switching time and reduces dynamic switching losses.

摘要翻译： 它公开了一种用于串联和/或并联连接的功率半导体开关（S1 ... S4）的动态Belastungssymmetrisierung的方法。 功率半导体开关各个开关信号（IG1，IG2）（S1 ... S4）是由一个全系统的有效同步采样时间（TSJ）独立地为一个同步事件（ES）的基础上，每个功率半导体开关（S1 ... S4）产生的（整个电路的 1，4）被确定。 采样时间（TSJ）之间的偏差同时测得的实际值（AI）和预定目标值的功率半导体开关的异步状态变量（（t））的（按）（S1 ... S4）可以在同一或随后的操作循环降低。 可替代地，时间的实际值（TAI）和时间的设定值（TAS）之间的控制偏差被最小化，其中所述时间 - 实际值（TAI）超过全球预定的阈值时（ε-a）一种异步状态变量的功率半导体开关的（A（t））的（S1 ... S4）被测量。 实施方案涉及：通过平均实际值（AI，泰），异步状态变量（一个（t））的梯度的附加对称本地或全球移采样（TSJ）是全球性的预先确定的时间间隔（DELTA吨0），设定点值，例如。 中央采样命令被消除，并且它可以切换缩短同步改进的响应时间和动态开关损耗降低。

公开(公告)号：WO02051006A1

公开(公告)日：2002-06-27

申请号：PCT/DE2001/004781

申请日：2001-12-19

IPC分类号： G11C17/18 ,  H03K3/356 ,  H03K5/02 ,  H03K17/10 ,  H03K19/0185 ,  H03K19/094

CPC分类号： G11C17/18 ,  H03K3/356113 ,  H03K5/02 ,  H03K17/102

摘要： A circuit arrangement for level amplification, in particular for controlling a connection (1), programmable with an energy impulse is disclosed, which may also be characterised as a fuse. The circuit arrangement comprises a circuit for level amplification (25) and a logic circuit (7). The logic circuit connects a first input signal to a second input signal (A, B) and controls an input for the level amplification circuit (25), whereby the output level of an output signal from the circuit for level amplification is greater than the input level. A fusible connection (1) may be connected to an output connector for the circuit for level amplification (25). As an input stage (N1, N3) of the circuit for level amplification (25) is also a first partial circuit of the logic circuit (7), said circuit arrangement permits a particularly component- and space-saving construction. The above is of particular advantage in mass-memory chips.

摘要翻译： 它是电平升压电路，特别是用于驱动一个可编程以指定的能量脉冲的化合物（1），其也被称作熔丝。 该电路装置包括：用于水平升压（25）和逻辑电路（7）的电路。 与第一到第二输入信号（A，B）相关联的逻辑电路和控制用于（25）电平升压电路的输入端，用于电平升压比输入电平较大的电路的输出信号的输出电平。 熔线（1）可连接到所述升压电路，用于电平（25）的输出端子。 作为升压的同时进行电平电路的输入级（N1，N3）（25）的逻辑电路（7）的第一子电路，该电路布置使得一个特殊的部件和节省空间的结构。 位于大容量存储芯片时，这具有特别有利的。

公开(公告)号：WO02027920A1

公开(公告)日：2002-04-04

申请号：PCT/EP2001/010973

申请日：2001-09-18

IPC分类号： H03F3/21 ,  H03F1/22 ,  H03F3/193 ,  H03K17/082 ,  H03K17/10

CPC分类号： H03F1/523 ,  H03F1/223

摘要： A cascode bootstrapped analog power amplifier circuit (1) includes a first MOSFET (10) and a second MOSFET (12) connected in series and coupled between a dc voltage source terminal (14) and a common terminal (gnd). An rf input signal terminal (18) is coupled to a gate electrode of the first MOSFET (10) and a dc control voltage terminal (26) is coupled to a gate electrode of the second MOSFET (12), with a unidirectionally-conducting element (32) such as a diode-connected MOSFET being coupled between a drain electrode and the gate electrode of the second MOSFET (12). The output of the amplifier circuit (1) is taken from the drain electrode of the second MOSFET (12). This circuit configuration permits the first and second MOSFETs to withstand a larger output voltage swing, thus permitting the use of a higher supply voltage and resulting in a substantially increased maximum output power capability for a given load value.

摘要翻译： 级联自举模拟功率放大器电路（1）包括串联连接并耦合在直流电压源端子（14）和公共端子（gnd）之间的第一MOSFET（10）和第二MOSFET（12）。 RF输入信号端子（18）耦合到第一MOSFET（10）的栅电极，并且直流控制电压端子（26）被耦合到第二MOSFET（12）的栅电极，具有单向导电元件 （32），例如耦合在漏电极和第二MOSFET（12）的栅电极之间的二极管连接的MOSFET。 放大电路（1）的输出取自第二MOSFET（12）的漏电极。 该电路配置允许第一和第二MOSFET承受更大的输出电压摆幅，从而允许使用更高的电源电压，并且对于给定的负载值，导致基本上增加的最大输出功率能力。

公开(公告)号：WO99065130A1

公开(公告)日：1999-12-16

申请号：PCT/US1999/009672

申请日：1999-05-03

IPC分类号： A61K31/568 ,  A61K31/565 ,  A61K31/5685 ,  A61P3/04 ,  A61P3/10 ,  A61P5/24 ,  A61P9/00 ,  A61P9/10 ,  A61P13/00 ,  A61P13/08 ,  A61P15/00 ,  A61P15/10 ,  A61P15/12 ,  A61P17/00 ,  A61P19/10 ,  A61P25/28 ,  A61P35/00 ,  A61P43/00 ,  C07J1/00 ,  H03K17/082 ,  H03K17/10 ,  H03K19/003 ,  H02H1/00 ,  H02H1/04 ,  H02H3/00 ,  H02H3/20 ,  H02H3/22 ,  H02H3/24 ,  H02H5/00 ,  H02H9/00 ,  H02H9/04 ,  H02H9/06 ,  H03B1/00 ,  H03K17/16 ,  H03K17/30 ,  H03K19/0175 ,  H03K19/094

CPC分类号： H03K17/0822 ,  H03K17/102 ,  H03K19/00315

摘要： Briefly, in accordance with one embodiment of the invention, an integrated circuit (IC) includes: a stress-follower circuit configuration (100). The stress-follower circuit (110) of the configuration is coupled to a pad (150) of the integrated circuit. The stress-follower circuit configuration is coupled so as to reduce the voltage stress on the gate of a transistor in the stack tolerates an operating voltage approximately 1.5 volts above its nominal voltage. The transistor stack (120, 130) is also coupled to the pad.

摘要翻译： 简而言之，根据本发明的一个实施例，集成电路（IC）包括：应力跟随器电路配置（100）。 该结构的应力跟随器电路（110）耦合到集成电路的焊盘（150）。 应力跟随器电路配置被耦合以便减小堆叠中的晶体管的栅极上的电压应力容许高于其额定电压大约1.5伏的工作电压。 晶体管堆叠（120,130）也耦合到焊盘。

公开(公告)号：WO99035695A1

公开(公告)日：1999-07-15

申请号：PCT/DE1998/003592

申请日：1998-12-07

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786 ,  H03K17/10

CPC分类号： H01L29/66681 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66674 ,  H01L29/7394 ,  H01L29/7824 ,  H03K17/102

摘要： The invention relates to a silicon-on-insulator high-voltage switch with a field effect transistor structure. The invention provides for a drift zone (11) of the one conductivity type to be located in the drain area (3, 2) between a gate electrode (6) and a drain electrode (7, D). Column-like grooves (8) having the form of a grid are embedded in said drift zone (11) and filled with semi-conductor material (9, 10) of the other conductivity type.

摘要翻译： 本发明涉及一种具有场效应晶体管结构，其中栅电极（6）和在所述漏极区域的漏电极（7，D）之间的（3，2）具有的，提供了一种导电类型的漂移区（11）的SOI高压开关。 在此漂移区（11）被嵌入在一个网格的形式柱状沟槽（8），与所述另一种导电类型的半导体材料（9，10）被填充。

公开(公告)号：WO9819398A3

公开(公告)日：1998-07-23

申请号：PCT/IB9701195

申请日：1997-10-02

申请人： PHILIPS ELECTRONICS NV ,  PHILIPS NORDEN AB

发明人： WONG STEPHEN L

IPC分类号： H03K17/10 ,  H03K17/06 ,  H03K17/16 ,  H03K17/687

CPC分类号： H03K17/6871 ,  H03K17/063

摘要： An integrated half-bridge timing control circuit for driving a half-bridge output stage has high-side and low-side power transistors coupled together at a high-voltage output terminal, and a bistable circuit for generating a high-side timing control waveform. The bistable circuit is driven by two delay circuits, each of which is decoupled from the high-side voltage by an associated interface circuit. The interface circuits are driven by input voltages which are delayed with respect to each other and which are referenced to the low side (ground). In this manner, an integrated half-bridge timing control circuit is obtained which is capable of operating at high frequencies with little power loss, which can be easily integrated, and which is both accurate and easily adjustable in operation.

公开(公告)号：WO1997044900A1

公开(公告)日：1997-11-27

申请号：PCT/DE1997000940

申请日：1997-05-09

申请人： SIEMENS AKTIENGESELLSCHAFT ,  TIHANYI, Jenö

发明人： SIEMENS AKTIENGESELLSCHAFT

IPC分类号： H03K17/10

CPC分类号： H03K17/6871 ,  H02M3/33569 ,  H02M2001/0006 ,  H03K17/102

摘要： This invention concerns a combinational circuit device comprising a power MOS-FET, the load link of which is connected in series to a wire wound coil of a repeater, as well as a gate voltage supply circuit, the output signal of which is directed to the gate terminal of the power MOS-FET, in which the power MOS-FET (1) is a high voltage MOS-FET and there are a second MOS-FET (2), the load link of which is connected in series to the load link of high voltage MOS-FET (1) with low ohm construction, and a control circuit (14), which is fed from the signal applied to the gate terminal (G1) of the high voltage MOS-FET (1) and produces a signal for controlling the second MOS-FET (2).

摘要翻译： 开关电源的功率MOSFET，其负载路径串联连接有线圈绕组的变压器，以及栅极电压供应电路，其输出信号被提供到功率MOSFET的栅极，功率MOSFET（1）是一种高电压MOSFET和第二 MOSFET（2）被提供，其负载路径串联连接在高电压MOSFET的负载路径（1）和其低阻抗的形成，从高电压MOSFET的栅极端子（G1）抵接的控制电路（14）（1） 信号的供给和生成用于驱动所述第二MOSFET（2）的信号。

公开(公告)号：WO1996023356A1

公开(公告)日：1996-08-01

申请号：PCT/DE1995001875

申请日：1995-12-29

申请人： SIEMENS AKTIENGESELLSCHAFT ,  HANNEBERG, Armin ,  TEMPEL, Georg

发明人： SIEMENS AKTIENGESELLSCHAFT

IPC分类号： H03K17/10

CPC分类号： G11C5/143 ,  G11C5/14 ,  G11C16/12 ,  G11C16/14 ,  H03K3/356017 ,  H03K3/356147 ,  H03K17/102 ,  H03K17/693

摘要： The invention concerns a MOS circuit for switching high voltages on a semiconductor chip. In order to switch a high negative voltage (-Vpp), for example as a programming voltage on the word line of a flash-memory, two circuit variants are given which are formed only with transistors of the same type of conduction as the substrate. In this way it is possible to dispense with deep insulating tanks which require special technology.

摘要翻译： 用于切换高的负电压（-VPP），例如作为一个编程电压施加到快闪存储器的字线，被指定两种类型的电路装置，其与晶体管为同一导电类型的衬底上形成。 这使得有可能与需要特殊工艺深水井绝缘免除。

公开(公告)号：WO1984003185A1

公开(公告)日：1984-08-16

申请号：PCT/US1983001997

申请日：1983-12-15

申请人： MOTOROLA, INC.

发明人： MOTOROLA, INC. ,  HUNTINGTON, Robert, C.

IPC分类号： H03K17/10

CPC分类号： G05F3/205

摘要： An integrated circuit and method includes a substrate bias voltage control circuit (20) formed on a common substrate therewith for ensuring that the substrate has a voltage (VCC or VBB) applied thereto while a semiconductor device on the substrate has a supply voltage (VCC) applied thereto which includes means for providing sources of bias (30) and supply (28) voltages to the substrate with means for firstly coupling the bias voltage to the substrate when the bias voltage is present and means for secondly coupling the supply voltage to the substrate when the bias voltage is not present.