公开(公告)号：WO1994029903A1

公开(公告)日：1994-12-22

申请号：PCT/US1994006259

申请日：1994-06-02

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  WEI, Yi-Hen

IPC: H01L29/73

CPC classification number: H01L29/0804 ,  H01L21/8249 ,  Y10S148/011

Abstract: The present invention provides a BiCMOS integrated circuit (100) with bipolar (110), NMOS (112) and PMOS (114) transistors. In a bipolar transistor, an emitter buffer (164) is provided to minimize a hot carrier effect. The emitter buffer is implanted using the same mask used for a base link (146). However, the n-type dopant is implanted using a large angle, while the p-type dopant is implanted using a normal implant. A "base" oxide (170) is grown over the implant region. This oxide ultimate isolates the emitter buffer from the polysilicon emitter contact section (160). Local interconnects (180) are formed using a "split-poly" technique, in which a tungsten silicide cap layer (184) is formed over polysilicon to short pn junctions in the interconnect.

Abstract translation: 本发明提供了具有双极（110），NMOS（112）和PMOS（114）晶体管的BiCMOS集成电路（100）。 在双极晶体管中，提供发射极缓冲器（164）以最小化热载流子效应。 使用用于基本链路（146）的相同掩模来注入发射器缓冲器。 然而，使用大角度注入n型掺杂剂，而使用普通植入物注入p型掺杂剂。 在植入区域上生长“碱”氧化物（170）。 该氧化物最终将发射极缓冲器与多晶硅发射极接触部分（160）隔离。 使用“分裂多晶”技术形成局部互连（180），其中在多晶硅上形成硅化钨覆盖层（184）以在互连中短路pn结。

公开(公告)号：WO1994029797A1

公开(公告)日：1994-12-22

申请号：PCT/US1994006009

申请日：1994-05-27

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  JIRGAL, James, J. ,  EVOY, David, R. ,  POTTS, Walter, H.

IPC: G06F13/36

CPC classification number: G06F13/362

Abstract: A computer system (10) having a multiplex address/data bus with a multiplex system controller (18) and method therefor is disclosed which provides in a computer system (10) having time shared use of a multiplex address/data bus to reduced the number of required pins for devices within the computer system (10), a CPU (12) having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information. In addition, this system (10) includes at least one memory input/output device (14) coupled to a first portion of the address bus for sending and receiving at least one of address information and data information, at least one input/output only device (16) coupled to a second portion of the address bus for sending and receiving at least one of address information and data information, and a multiplex system controller (18) coupled to the CPU (12) and the address bus and having a multiplex control bus coupled to both the memory input/output device (14) and to the input/output only device (16) for taking control of the address bus from the CPU (12).

Abstract translation: 公开了一种具有多路复用地址/数据总线的计算机系统（10），其具有多路复用系统控制器（18）及其方法，其在计算机系统（10）中提供多路复用地址/数据总线的时间共享使用以减少数量 用于计算机系统（10）内的设备的所需引脚，具有至少一个地址总线的CPU（12），至少一个数据总线，至少一个存储器输入/输出以及耦合到其上的至少一个CPU控制总线，用于发送 并接收信息。 此外，该系统（10）包括耦合到地址总线的第一部分的至少一个存储器输入/输出设备（14），用于发送和接收地址信息和数据信息中的至少一个，至少一个输入/输出 设备（16），其耦合到所述地址总线的第二部分，用于发送和接收地址信息和数据信息中的至少一个;以及多路复用系统控制器（18），耦合到所述CPU（12）和所述地址总线， 控制总线耦合到存储器输入/输出设备（14）和仅输入/输出设备（16），用于从CPU（12）控制地址总线。

公开(公告)号：WO1994027325A1

公开(公告)日：1994-11-24

申请号：PCT/US1994003815

申请日：1994-04-07

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  WEI, Yi-Hen ,  LOH, Ying, Tsong ,  WANG, Chung, S. ,  HU, Chenming

IPC: H01L29/784

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/7836

Abstract: An integrated circuit device including a substrate (12), a gate structure (10) formed over the substrate, a channel (C) formed in the substrate under the gate, a lightly-doped drain-side LDD region (22) formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region (30) formed in the substrate near to the drain-side LDD region, and a drain-side DDD region (34) substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region (20) is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region (28) is formed in the substrate near to the source-side LDD region, and a source-side DDD region (32) is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate. A method of the present invention includes the steps of providing a semiconductor substrate (12), forming a gate (10) over the substrate to define a channel (C), doping the substrate to form a pair of LDD regions (20/22) in the substrate, doping the substrate to form a drain region (30) and a source region (28), and doping the substrate to form a drain-side DDD region (34) in the substrate which substantially separates the drain region from the drain-side LDD region (22) and which substantially isolates the drain region from a bulk portion of the substrate, and to form a source-side DDD region (32) in the substrate which substantially separates the source region from the source-side LDD region (20) and substantially isolates the source region from a bulk portion of the substrate.

Abstract translation: 一种集成电路器件，包括衬底（12），形成在衬底上的栅极结构（10），形成在栅极下的衬底中的沟道（C），形成在衬底中的轻掺杂漏极侧LDD区（22） 与沟道的漏极侧相邻的衬底（优选通过LATID工艺），形成在衬底中的漏极侧LDD区域附近的漏极区域（30）和漏极侧DDD区域（34） 漏极侧LDD区域。 优选地，集成电路器件被对称地形成，使得在与衬底的源极侧相邻的衬底（再次优选地通过LATID工艺）中形成轻掺杂的源极侧LDD区域（20），源极区域 28）形成在靠近源极侧LDD区域的衬底中，并且在衬底中形成源极DDD区域（32），以将源极侧LDD区域与源极区域基本分离。 更优选地，DDD区域基本上将源极和漏极与基板的主体部分隔离。 本发明的方法包括以下步骤：提供半导体衬底（12），在衬底上形成栅极（10）以限定通道（C），掺杂衬底以形成一对LDD区域（20/22） 在衬底中掺杂衬底以形成漏极区域（30）和源极区域（28），并且掺杂衬底以在衬底中形成基本上将漏极区域与漏极区分开的漏极侧DDD区域（34） （22），并且基本上将漏极区域与衬底的本体部分隔离，并且在衬底中形成源极区域DDD区域（32），其基本上将源极区域与源极侧LDD区域分离 （20）并且基本上将源极区域与衬底的本体部分隔离。

公开(公告)号：WO1994019699A1

公开(公告)日：1994-09-01

申请号：PCT/US1994001653

申请日：1994-02-16

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  TOPSAKAL, Michael, A. ,  HUANG, Chin-Ching

IPC: G01R01/04

CPC classification number: G01R1/04 ,  G01R1/0483

Abstract: Using a Z-axis material (12'), a bare die (36) can be burn-in tested without first packaging the die. Burn-in testing of the bare die has the benefit of saving packaging efforts. For multiple die packages, burn-in testing of the bare die has the benefit that each individual die can be burn-in tested separately from the package.

Abstract translation: 使用Z轴材料（12'），裸模（36）可以在不首先封装模具的情况下进行老化测试。 裸机的老化测试有利于节省包装工作。 对于多个管芯封装，裸裸片的老化测试具有以下优点：每个单独的裸片可以与封装分开测试。

公开(公告)号：WO1994006154A1

公开(公告)日：1994-03-17

申请号：PCT/US1993008549

申请日：1993-09-10

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  LIANG, Louis, H.

IPC: H01L23/433

CPC classification number: H01L23/4334 ,  H01L23/49568 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/49121 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A molded plastic package (40) for an integrated-circuit die (26) includes a lead frame having a central die-attach paddle (12). One side of the die-attach paddle has an integrated-circuit die fixed thereto. A heat sink member (20) is resiliently fixed to the other side of the die-attach paddle using a layer of viscous thermal grease (24) between the heat sink member and the other side of the die-attach paddle. One or more holes which are formed in the lead frame are engaged by corresponding studs (24C, 24D) on the heat sink. The stud has a shoulder portion (74) which engages the lead frame to prevent the stud from further passing through the hole in the lead frame.

Abstract translation: 一种用于集成电路管芯（26）的模制塑料封装（40）包括具有中心管芯附着焊盘（12）的引线框架。 管芯附接板的一侧具有固定到其上的集成电路管芯。 散热构件（20）使用在散热构件和芯片附接板的另一侧之间的一层粘性导热油脂（24）弹性地固定到模片附接桨的另一侧。 形成在引线框架中的一个或多个孔与散热器上的相应螺柱（24C，24D）接合。 螺柱具有接合引线框架的肩部（74），以防止螺柱进一步穿过引线框架中的孔。

公开(公告)号：WO1993026043A1

公开(公告)日：1993-12-23

申请号：PCT/US1993005218

申请日：1993-06-04

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  WELING, Milind ,  JAIN, Vivek

IPC: H01L21/90

CPC classification number: H01L21/31116 ,  H01L21/76819

Abstract: A method for planarization of a semiconductor process material that contains exposed surfaces of an oxide of silicon and a spin-on-glass (SOG). The oxide of silicon is chosen to be oxygen-deficient and thus silicon-rich, with a spectroscopically-defined silicon richness coefficient CSR that is greater than 0, and preferably at least equal to 0.005. A fluorine-containing, oxygen-free process gas, such as CHF3 with CF4 or C2F6 or SF6 added, may be used for the etchant or process gas.

Abstract translation: 一种用于平面化半导体工艺材料的方法，其包含硅和旋涂玻璃（SOG）的氧化物的暴露表面。 硅的氧化物选择为缺氧的，因此富含硅，其光谱定义的硅富集系数CSR大于0，优选至少等于0.005。 可以使用含氟，无氧工艺气体，例如加入CF4或C2F6或SF6的CHF3，用于蚀刻剂或工艺气体。

公开(公告)号：WO1993023937A1

公开(公告)日：1993-11-25

申请号：PCT/US1992004080

申请日：1992-05-14

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  EBZERY, Thomas

IPC: H04L07/027

CPC classification number: H03L7/00 ,  H04L7/0338

Abstract: A digital signal phase adjustment circuit adjusts the phase of a data signal in relation to a first local clock signal having a frequency of f. Also provided is a second local clock signal with a frequency of Nf, where N is a positive integer greater than 1. An N-bit shift register (120), clocked by the second local clock signal, generates N phase signals that are enabled in rotating sequential order during non-overlapping time intervals. One of the N phase signals is selected by a multiplexer (130) and used as the enable control signal for a data sampling circuit that is clocked by the second local clock signal. The data sampling circuit samples and outputs the data signal only when the selected phase signal is enabled, thereby outputting the data signal with a selected phase relative to the first clock signal.

Abstract translation: 数字信号相位调整电路相对于具有频率f的第一本地时钟信号来调整数据信号的相位。 还提供了频率为Nf的第二本地时钟信号，其中N是大于1的正整数。由第二本地时钟信号计时的N位移位寄存器（120）产生N相位信号， 在非重叠时间间隔期间旋转顺序。 N相信号中的一个由多路复用器（130）选择，并用作由第二本地时钟信号计时的数据采样电路的使能控制信号。 数据采样电路仅在选择的相位信号使能时对数据信号进行采样和输出，从而以相对于第一时钟信号的选定相位输出数据信号。

公开(公告)号：WO1993020501A1

公开(公告)日：1993-10-14

申请号：PCT/US1993000973

申请日：1993-02-04

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  CAVIASCA, Ken ,  MATTISON, Ken

IPC: G06F07/38

CPC classification number: H03M7/16 ,  G06F7/5443

Abstract: A device and method for converting 18-bit RGB data to 5-bit gray scale data is disclosed. This device and method comprise a barrel shifter (12), an adder (14), a palette storage register (16), and control logic (18). The red data is loaded first into the barrel shifter (12), and is shifted, added and stored in the palette storage register (16). The green data is then loaded into the barrel shifter (12) and is shifted and added to the value stored in the palette storage register (16). The blue data is then loaded into the barrel shifter (12) and is shifted and added to the value stored in the palette storage register (16), thereby completing the conversion. The five most significant bits of the six-bit palette storage register (16) are output as gray scale data. The shifting and adding of these six-bit integers allow a binary approximation of the appropriate coefficients for each block of color data.

公开(公告)号：WO1993018468A1

公开(公告)日：1993-09-16

申请号：PCT/US1993001747

申请日：1993-02-25

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  MISHELOFF, Michael, N.

IPC: G06F15/60

CPC classification number: G06F17/5022

Abstract: A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value. The second formula also varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device.

Abstract translation: 一种方法通过逻辑器件近似传播延迟。 逻辑器件的操作被分为第一区域和第二区域。 第一区域和第二区域之间的边界基于逻辑器件的输入斜坡的持续时间和逻辑器件驱动的容性负载量。 例如，发生第一区域和第二区域之间的边界，对于容性负载的每个值，当输入斜坡完成时，逻辑器件的输出斜坡为一半。 当逻辑设备在第一区域中操作时，使用第一公式来获得表示通过逻辑设备的延迟的第一值。 第一个公式根据逻辑器件输入斜坡的持续时间和由逻辑器件驱动的容性负载来改变第一个值。 当逻辑设备在第二区域中操作时，使用第二公式来获得第一值。 第二个公式还根据逻辑器件输入斜坡的持续时间和由逻辑器件驱动的容性负载来改变第一个值。

公开(公告)号：WO9317455A2

公开(公告)日：1993-09-02

申请号：PCT/US9301490

申请日：1993-02-19

Applicant: VLSI TECHNOLOGY INC

Inventor： KWON YOUNG IL ,  LIANG LOUIS H

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/498 ,  H01L23/50

CPC classification number: H01L23/495 ,  H01L23/49531 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20654 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A package design configuration for an integrated-circuit die (104) includes a leadframe having its bonding fingers (106) connected to the periphery of an electrically-insulated, heat-conductive substrate (102), formed, for example, of a ceramic material. A number of electrically conductive traces (110), or bonding islands, serve as intermediate bonding locations for shorter bonding wires (112, 116) connecting bonding pads (114) on the integrated-circuit die (104) to the bonding fingers (106) of the leadframe. The integrated-circuit die overlies the conductive traces while still providing an exposed portion of the conductive traces as a respective intermediate attachment area for respective bonding wires. The conductive traces serving as bonding islands are formed by deposition of thin-film material using semiconductor fabrication techniques or by deposition of thick-film material using printing techniques.

Abstract translation: 用于集成电路管芯（104）的封装设计构造包括引线框架，其具有连接到电绝缘的导热基板（102）的外围的接合指状物（106），所述引线框架例如由陶瓷材料 。 多个导电迹线（110）或接合岛用作将集成电路管芯（104）上的接合焊盘（114）连接到接合指状物（106）的较短接合线（112,116）的中间接合位置， 的引线框架。 集成电路管芯覆盖导电迹线，同时仍然将导电迹线的暴露部分作为相应接合线的相应的中间附接区域。 用作结合岛的导电迹线通过使用半导体制造技术沉积薄膜材料或通过使用印刷技术沉积厚膜材料而形成。