公开(公告)号：WO2008061128A3

公开(公告)日：2008-05-22

申请号：PCT/US2007/084650

申请日：2007-11-14

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TESSMER, Glenn, J. ,  HORTALEZA, Edgardo, R. ,  BRIGGS, Thad, E.

Inventor： TESSMER, Glenn, J. ,  HORTALEZA, Edgardo, R. ,  BRIGGS, Thad, E.

IPC: H01L21/4763

Abstract: A semiconductor device having copper interconnecting metallization (111) protected by a first (102) and a second (120) overcoat layer (homogeneous silicon dioxide), portions of the metallization exposed in a window (103) opened through the thicknesses of the first and second overcoat layers. A patterned conductive barrier layer (130) is positioned on the exposed portion of the copper metallization and on portions of the second overcoat layer surrounding the window. A bondable metal layer (150) is positioned on the barrier layer; the thickness of this bondable layer is suitable for wire bonding. A third overcoat layer (160) consist of a homogeneous silicon nitride compound is positioned on the second overcoat layer so that the ledge (162, more than 500 nm high) of the third overcoat layer overlays the edge (150b) of the bondable metal layer. The resulting contoured chip surface improves the adhesion to plastic device encapsulation.

公开(公告)号：WO2008061128A2

公开(公告)日：2008-05-22

申请号：PCT/US2007084650

申请日：2007-11-14

Applicant: TEXAS INSTRUMENTS INC ,  TESSMER GLENN J ,  HORTALEZA EDGARDO R ,  BRIGGS THAD E

Inventor： TESSMER GLENN J ,  HORTALEZA EDGARDO R ,  BRIGGS THAD E

IPC: H01L21/56 ,  H01L23/50

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/00

Abstract: A semiconductor device having copper interconnecting metallization (111) protected by a first (102) and a second (120) overcoat layer (homogeneous silicon dioxide), portions of the metallization exposed in a window (103) opened through the thicknesses of the first and second overcoat layers. A patterned conductive barrier layer (130) is positioned on the exposed portion of the copper metallization and on portions of the second overcoat layer surrounding the window. A bondable metal layer (150) is positioned on the barrier layer; the thickness of this bondable layer is suitable for wire bonding. A third overcoat layer (160) consist of a homogeneous silicon nitride compound is positioned on the second overcoat layer so that the ledge (162, more than 500 nm high) of the third overcoat layer overlays the edge (150b) of the bondable metal layer. The resulting contoured chip surface improves the adhesion to plastic device encapsulation.

Abstract translation: 具有由第一（102）和第二（120）外涂层（均匀二氧化硅）保护的铜互连金属化（111）的半导体器件，暴露在窗口（103）中的金属化部分暴露在第一和/ 第二层涂层。 图案化的导电阻挡层（130）被定位在铜金属化的暴露部分上以及围绕窗口的第二覆盖层的部分上。 可粘合金属层（150）位于阻挡层上; 该可结合层的厚度适合于引线接合。 由均匀的氮化硅化合物构成的第三外涂层（160）位于第二外涂层上，使得第三外涂层的凸缘（162，大于500nm高）覆盖在可结合金属层的边缘（150b）上 。 所形成的轮廓芯片表面改善了对塑料器件封装的粘附性。

公开(公告)号：WO2008144621A1

公开(公告)日：2008-11-27

申请号：PCT/US2008/064071

申请日：2008-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MATZ, Laura, M. ,  TSUI, Ting, Y. ,  BRIGGS, Thad, E. ,  KRAFT, Robert

Inventor： MATZ, Laura, M. ,  TSUI, Ting, Y. ,  BRIGGS, Thad, E. ,  KRAFT, Robert

IPC: H01L21/28

CPC classification number: H01L21/3148 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834

Abstract: In accordance with the principles of the invention, semiconductor devices (100) and methods of making semiconductor devices and dielectric stack (101) in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure (170) including one or more copper interconnects and forming an etch stop layer (110) over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer (120) over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer (130) over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

Abstract translation: 根据本发明的原理，提供半导体器件（100）以及在集成电路中制造半导体器件和电介质叠层（101）的方法。 在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构（170），并在第一处理室中在半导体结构上形成蚀刻停止层（110）。 该方法还可以包括在第一处理室中的蚀刻停止层上形成薄氧化硅层（120），并在第二处理室中在薄氧化硅层上形成超低k电介质层（130），其中形成 与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质叠层相比，薄的氧化硅层改善了蚀刻停止层和超低k电介质之间的粘合性。