公开(公告)号：WO2009026171A3

公开(公告)日：2009-02-26

申请号：PCT/US2008/073365

申请日：2008-08-15

Applicant: VERTICAL CIRCUITS, INC. ,  CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott ,  ROBINSON, Marc ,  SCOTT, Mark ,  DU, Yong ,  JONES, Roydn ,  TRAN, Thanh, Van

Inventor： CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott ,  ROBINSON, Marc ,  SCOTT, Mark ,  DU, Yong ,  JONES, Roydn ,  TRAN, Thanh, Van

IPC: H01L23/12

Abstract: Apparatus for making electrical interconnection of semiconductor die includes a transfer carrier having an electrically conductive material arranged in a pattern on a transfer surface. A transfer process for electrical interconnect includes steps of aligning the transfer apparatus with an edge of a die to be interconnected; and moving the transfer apparatus toward the die edge (or moving the die edge toward the transfer apparatus, or moving both the transfer carrier and the die edge in relation to one another) to bring the patterned conductive material on the transfer surface and interconnect terminals on the die into contact. In some embodiments the carrier is left in place in a functioning interconnected device; in other embodiments the transfer carrier and the die edge are separated to leave at least a portion of the conductive material in contact with the interconnect terminals.

公开(公告)号：WO2008157779A2

公开(公告)日：2008-12-24

申请号：PCT/US2008/067722

申请日：2008-06-20

Applicant: VERTICAL CIRCUITS, INC. ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.S. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong

Inventor： ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.S. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong

IPC: H01L27/00 ,  H01L27/10

CPC classification number: G01R1/0483 ,  H01L24/02 ,  H01L24/16 ,  H01L24/31 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2224/03

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g., die-to-substrate); and assemblies including a stack of at least two such devices interconnected die-to-die, or such a stack of devices electrically interconnected to underlying circuitry. Also, apparatus and methods for testing such a die.

Abstract translation: 可堆叠集成电路器件包括具有在有源（正面）侧上的互连焊盘的集成电路管芯，该管芯具有在管芯的前侧和管芯侧壁的连接处的前侧边缘， 模具的背面与侧壁的结合; 芯片还包括电连接到互连焊盘并且在模具的前侧边缘上延伸的导电迹线。 在一些实施例中，导电迹线还在侧壁上延伸，并且在一些这样的实施例中，导电迹线还在模具的背侧边缘上延伸，并且在一些这样的实施例中，导电迹线还在模具的背面延伸。 一个或两个模边可被倒角。 另外，制造这种装置的方法。 而且，包括这样的器件的组件电连接到底层电路（例如，裸片到衬底）; 以及包括至少两个这样的设备的堆叠的组件，这些设备互相连接到芯片上，或者这样一组电器件互连到下面的电路。 另外，用于测试这种模具的装置和方法。

公开(公告)号：WO2008154582A3

公开(公告)日：2008-12-18

申请号：PCT/US2008/066568

申请日：2008-06-11

Applicant: VERTICAL CIRCUITS, INC. ,  MCGRATH, Scott ,  CASKEY, Terrence ,  MCELREA, Simon, J.s. ,  ANDREWS, Lawrence, Douglas ,  LIU, Zongrong

Inventor： MCGRATH, Scott ,  CASKEY, Terrence ,  MCELREA, Simon, J.s. ,  ANDREWS, Lawrence, Douglas ,  LIU, Zongrong

IPC: H01L23/02 ,  H01L21/673 ,  H01L23/28

Abstract: Fixtures for temporarily holding semiconductor die and for holding stacked die units, for application of a material such as electrical interconnection material to die edges, include a fixture frame, die or die stack supports, and a mask. Methods for applying material such as electrical interconnection material to die edges and to die stack units employ the fixtures using a mask lift-off step.

公开(公告)号：WO2008154580A2

公开(公告)日：2008-12-18

申请号：PCT/US2008/066561

申请日：2008-06-11

Applicant: VERTICAL CIRCUITS, INC. ,  MCGRATH, Scott ,  MCELREA, Simon, J.s. ,  CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  DU, Yong

Inventor： MCGRATH, Scott ,  MCELREA, Simon, J.s. ,  CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  DU, Yong

IPC: H01L23/12

CPC classification number: H01L25/50 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01038

Abstract: A method for forming electrical interconnection on stacked die units includes steps of arranging one or more stacked die units so that the arrangement presents die edges to be interconnected at a stack face, and applying a trace of electrical interconnect material at the presented stack face.

Abstract translation: 一种用于在堆叠的模具单元上形成电互连的方法包括以下步骤：布置一个或多个堆叠的模具单元，使得该布置使得模具边缘在堆叠面处互连，并且在所呈现的堆叠面处施加一列电互连材料。

公开(公告)号：WO2011056987A3

公开(公告)日：2011-05-12

申请号：PCT/US2010/055472

申请日：2010-11-04

Applicant: VERTICAL CIRCUITS, INC. ,  McGRATH, Scott ,  LEAL, Jeffrey, S. ,  SHENOY, Ravi ,  CANTILLEP, Loreto ,  McELREA, Simon, J.S. ,  PANGRLE, Suzette, K.

Inventor： McGRATH, Scott ,  LEAL, Jeffrey, S. ,  SHENOY, Ravi ,  CANTILLEP, Loreto ,  McELREA, Simon, J.S. ,  PANGRLE, Suzette, K.

IPC: H01L23/48 ,  H01L23/12

Abstract: Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

公开(公告)号：WO2010151578A3

公开(公告)日：2010-12-29

申请号：PCT/US2010/039639

申请日：2010-06-23

Applicant: VERTICAL CIRCUITS, INC. ,  CO, Reynaldo ,  VILLAVICENCIO, Grant ,  LEAL, Jeffrey ,  McELREA, Simon, J.S.

Inventor： CO, Reynaldo ,  VILLAVICENCIO, Grant ,  LEAL, Jeffrey ,  McELREA, Simon, J.S.

IPC: H01L23/48 ,  H01L23/12

Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate.

公开(公告)号：WO2009114670A2

公开(公告)日：2009-09-17

申请号：PCT/US2009/036921

申请日：2009-03-12

Applicant: VERTICAL CIRCUITS, INC. ,  McELREA, Simon, J.S. ,  ROBINSON, Marc, E. ,  ANDREWS, Lawrence, Douglas, Jr.

Inventor： McELREA, Simon, J.S. ,  ROBINSON, Marc, E. ,  ANDREWS, Lawrence, Douglas, Jr.

IPC: H01L23/12 ,  H01L23/04

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L23/48 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L29/0657 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/00

Abstract: Stacked die assemblies are electrically connected to connection sites on any support, without electrical connection to an interposed substrate or leadframe, and without solder.

Abstract translation: 堆叠模具组件电连接到任何支撑件上的连接位置，没有电连接到插入的衬底或引线框架，也没有焊接。

公开(公告)号：WO2009052150A1

公开(公告)日：2009-04-23

申请号：PCT/US2008/079948

申请日：2008-10-15

Applicant: VERTICAL CIRCUITS, INC. ,  MCELREA, Simon, J.S. ,  ROBINSON, Marc, E. ,  ANDREWS, Lawrence, Douglas ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong ,  VINDASIUS, Al

Inventor： MCELREA, Simon, J.S. ,  ROBINSON, Marc, E. ,  ANDREWS, Lawrence, Douglas ,  CASKEY, Terrence ,  MCGRATH, Scott ,  DU, Yong ,  VINDASIUS, Al

IPC: H01L23/12

CPC classification number: H01L23/3114 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/24145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06572

Abstract: A die prepared for stacking in a chip scale stacked die assembly, having interconnect sites in an area inward from a die edge and interconnect pads near at least one die edge. Second-level interconnection of the stacked die assembly can be made by way of connections between a first die in the assembly and circuitry on a support; and interconnection between die in the stack can be made by way of connection of z-interconnects with bonds pads in the die attach side of the support near or at one or more die edges. Methods for preparing the die include processes carried out to an advanced stage at the wafer level or at the die array level.

Abstract translation: 准备用于堆叠在芯片级堆叠管芯组件中的管芯，其具有从管芯边缘向内的区域中的互连位置和在至少一个管芯边缘附近的互连焊盘。 可以通过组件中的第一管芯和支撑件上的电路之间的连接来进行堆叠管芯组件的二次互连; 并且堆叠中的管芯之间的互连可以通过z-互连与在支撑件的管芯附接侧中的接合焊盘附近或在一个或多个管芯边缘处的连接来进行。 制备模具的方法包括在晶片级或模具阵列级进行到高级阶段的工艺。

公开(公告)号：WO2009032371A1

公开(公告)日：2009-03-12

申请号：PCT/US2008/065788

申请日：2008-06-04

Applicant: VERTICAL CIRCUITS, INC. ,  CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott

Inventor： CASKEY, Terrence ,  ANDREWS, Lawrence, Douglas ,  MCELREA, Simon, J.s. ,  MCGRATH, Scott

IPC: H01L23/52 ,  H01L23/02

CPC classification number: H05K3/321 ,  H01L24/24 ,  H01L24/76 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/244 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K2203/0126 ,  H01L2224/82

Abstract: Methods for depositing interconnect material at a target for electrical interconnection include pulsed dispense of the material. In some embodiments droplets of interconnect material are deposited in a projectile fashion. In some embodiments the droplets are shaped by movement of the deposition tool following a deposition pulse and prior to separation of the droplet mass from the tool.

Abstract translation: 用于在用于电互连的靶上沉积互连材料的方法包括材料的脉冲分配。 在一些实施例中，互连材料的液滴以抛射体的方式沉积。 在一些实施例中，液滴通过沉积工具的运动在沉积脉冲之后并且在将液滴质量与工具分离之前成形。

公开(公告)号：WO2008157722A1

公开(公告)日：2008-12-24

申请号：PCT/US2008/067541

申请日：2008-06-19

Applicant: VERTICAL CIRCUITS, INC. ,  MCELREA, Simon, J.s. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  MELCHER, Deann, Eileen ,  CO, Reynaldo ,  ANDREWS, Lawrence, Douglas ,  PAN, Weiping ,  VILLAVICENCIO, Grant ,  DU, Yong ,  CRANE, Scott, Jay ,  LIU, Zongrong

Inventor： MCELREA, Simon, J.s. ,  CASKEY, Terrence ,  MCGRATH, Scott ,  MELCHER, Deann, Eileen ,  CO, Reynaldo ,  ANDREWS, Lawrence, Douglas ,  PAN, Weiping ,  VILLAVICENCIO, Grant ,  DU, Yong ,  CRANE, Scott, Jay ,  LIU, Zongrong

IPC: H01L21/76 ,  H01L21/78 ,  H01L23/02

CPC classification number: H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/2919 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract translation: 在晶片处理期间，电绝缘保形涂层至少施加到管芯的活性（前）侧和一个或多个侧壁。 此外，模具具有至少施加到活性（前）侧和侧壁的电绝缘保形涂层。 此外，组件包括这样的模具的堆叠，电互连的模 - 芯; 并且组件包括这样的管芯或这种管芯的堆叠，电连接到下面的电路（例如在衬底或电路板中）。