公开(公告)号：WO2013037240A1

公开(公告)日：2013-03-21

申请号：PCT/CN2012/078585

申请日：2012-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HARRER, Stefan ,  LUAN, Binquan ,  MARTYNA, Glenn J. ,  PENG, Hongbo ,  POLONSKY, Stanislav ,  ROSSNAGEL, Stephen M. ,  ROYYURU, Ajay K. ,  STOLOVITZKY, Gustavo A. ,  WALKER, George F.

Inventor： HARRER, Stefan ,  LUAN, Binquan ,  MARTYNA, Glenn J. ,  PENG, Hongbo ,  POLONSKY, Stanislav ,  ROSSNAGEL, Stephen M. ,  ROYYURU, Ajay K. ,  STOLOVITZKY, Gustavo A. ,  WALKER, George F.

IPC: G01N27/30

CPC classification number: B82Y15/00 ,  C12Q1/6869 ,  C12Q2565/631

Abstract: A technique for controlling the motion of one or more charged entities linked to a polymer through a nanochannel is provided. A first reservoir and a second reservoir are connected by the nanochannel. An array of electrodes is positioned along the nanochannel, where fluid fills the first reservoir, the second reservoir, and the nanochannel. A first electrode is in the first reservoir and a second electrode is in the second reservoir. The first and second electrodes are configured to direct the one or more charged entities linked to the polymer into the nanochannel. An array of electrodes is configured to trap the one or more charged entities in the nanochannel responsive to being controlled for trapping. The array of electrodes is configured to move the one or more charged entities along the nanochannel responsive to being controlled for moving.

Abstract translation: 提供了一种用于控制通过纳米通道连接到聚合物的一个或多个带电实体的运动的技术。 第一储存器和第二储存器通过纳米通道连接。 电极阵列沿纳米通道定位，其中流体填充第一储存器，第二储存器和纳米通道。 第一电极在第一储存器中，第二电极位于第二储存器中。 第一和第二电极被配置为将连接到聚合物的一个或多个带电实体引导到纳米通道中。 电极阵列被配置为捕捉纳米通道中的一个或多个带电实体，以响应于被捕获而被控制。 电极阵列被配置为响应于被控制移动而沿着纳米通道移动一个或多个带电实体。

公开(公告)号：WO2005041360A1

公开(公告)日：2005-05-06

申请号：PCT/US2003/030640

申请日：2003-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  VOLANT, Richard, P. ,  PETRARCA, Kevin, S. ,  WALKER, George, F.

Inventor： VOLANT, Richard, P. ,  PETRARCA, Kevin, S. ,  WALKER, George, F.

IPC: H01R12/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/9222 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.

Abstract translation: 描述了由多个折叠的集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片电连接的互连路径，并且至少一个芯片（130）是 具有附加到衬底（500），封装或印刷电路板的互连布线。 进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

公开(公告)号：WO2005062367A1

公开(公告)日：2005-07-07

申请号：PCT/US2003/037162

申请日：2003-11-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  PETRARCA, Kevin, S. ,  CHENG, Tien-Jen ,  KNICKERBOCKER, Sarah, H. ,  VOLANT, Richard, P. ,  WALKER, George, F.

Inventor： PETRARCA, Kevin, S. ,  CHENG, Tien-Jen ,  KNICKERBOCKER, Sarah, H. ,  VOLANT, Richard, P. ,  WALKER, George, F.

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05109 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05176 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/20754 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method of forming an input-output (I/0) structure is described, wherein a substrate having copper conductive feature (20) exposed at the bottom of a recess (25) in a first dielectric layer (10) is covered by a first conductive barrier (102) that is selectively formed in the recess (25). A second dielectric (105), preferably an organic polymer such as polyimide, is formed over the substrate surface and a second recess (27) is formed in the second dielectric (105) so that at least a portion of the first conductive barrier (102) is exposed. A second conductive barrier (107) is conformally deposited, followed by conformal deposition of a seed layer (109), where both are deposited under a vacuum to ensure adhesion of the seed layer (109) to the second conductive barrier (107). The seed layer (107) is selectively removed external to the recess (27), followed by plating of a nickel-containing metal (113) and then a noble metal (115), which will plate on the remaining portion of the seed layer (107) in the recess (27), but not on the second barrier layer (107). The second barrier layer (107) is removed from the exposed field areas by a low bias power RIE. The invention provides a low-cost method of forming an I/0 structure for both probe test and wire bond without damage to underlying devices and reduced chip real estate.

Abstract translation: 描述了形成输入 - 输出（I / O）结构的方法，其中在第一介电层（10）中的凹部（25）的底部露出的具有铜导电特征（20）的基板被第一 导电屏障（102），其选择性地形成在所述凹部（25）中。 第二电介质（105），优选有机聚合物（例如聚酰亚胺）形成在衬底表面上，并且第二凹陷（27）形成在第二电介质（105）中，使得至少一部分第一导电屏障（102 ）暴露。 第二导电屏障（107）被共形沉积，接着是晶种层（109）的共形沉积，其中两者都在真空下沉积以确保籽晶层（109）与第二导电屏障（107）的粘附。 种子层（107）被选择性地移除到凹部（27）的外部，然后镀覆含镍金属（113），然后镀覆贵金属（115），其将在种子层的剩余部分 107），但不在第二阻挡层（107）上。 通过低偏置功率RIE从曝光的场区域去除第二阻挡层（107）。 本发明提供了一种用于形成用于探针测试和线接合的I / O结构的低成本方法，而不损坏下面的器件并减少芯片的不动产。

公开(公告)号：WO2009134335A1

公开(公告)日：2009-11-05

申请号：PCT/US2009/002517

申请日：2009-04-23

Applicant: WALKER, George, F.

Inventor： WALKER, George, F.

IPC: G06F7/04

CPC classification number: A61K9/2072 ,  A61J3/007 ,  A61J2200/20 ,  A61J2205/10 ,  A61J2205/20 ,  A61J2205/40 ,  A61J2205/50

Abstract: The invention is an article of manufacture, comprising an identifying marker disposed in a pharmaceutical product. The pharmaceutical product may be selected from the group consisting of a pharmaceutical liquid, a pill, a tablet, a caplet, and a capsule. The identifying marker may be a hydroscopic medium having an indicia imprinted • thereon or within, where the marker expands volumetrically when contacted with a liquid..

Abstract translation: 本发明是一种制品，其包括设置在药品中的识别标记。 药物产品可以选自药物液体，丸剂，片剂，囊片和胶囊。 识别标记物可以是具有印记在其上或内部的标记的吸湿介质，其中当与液体接触时，标记物在体积上膨胀。

公开(公告)号：WO2009120404A1

公开(公告)日：2009-10-01

申请号：PCT/US2009/032339

申请日：2009-01-29

Applicant: IBM CORPORATION ,  HOVEL, Harold, J. ,  HUANG, Qiang ,  SHAO, Xiaoyan ,  VICHICONTI, James ,  WALKER, George, F.

Inventor： HOVEL, Harold, J. ,  HUANG, Qiang ,  SHAO, Xiaoyan ,  VICHICONTI, James ,  WALKER, George, F.

IPC: H01L21/00 ,  H01L31/06

CPC classification number: H01L31/18 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/02 ,  C30B29/06 ,  C30B29/40 ,  C30B29/52 ,  C30B29/60 ,  C30B29/605 ,  C30B33/10 ,  H01L21/30604 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L31/0352 ,  H01L33/20

Abstract: Segmented semiconductor nanowires are manufactured by removal of material from a layered structure of two or more semiconductor materials in the absence of a template. The removal takes place at some locations on the surface of the layered structure and continues preferentially along the direction of a crystallographic axis, such that nanowires with a segmented structure remain at locations where little or no removal occurs. The interface between different segments can be perpendicular to or at angle with the longitudinal direction of the nanowire.

Abstract translation: 在没有模板的情况下通过从两种或更多种半导体材料的层状结构中去除材料来制造分段半导体纳​​米线。 去除在层状结构的表面上的某些位置处发生，并且优选地沿着结晶轴的方向延伸，使得具有分段结构的纳米线保持在很少或不发生去除的位置。 不同片段之间的界面可以垂直于纳米线的纵向方向或与之相垂直。