公开(公告)号：WO2016205349A1

公开(公告)日：2016-12-22

申请号：PCT/US2016/037599

申请日：2016-06-15

Applicant: APPLIED MATERIALS, INC.

Inventor： ZENG, Weimin ,  NGUYEN, Thanh X. ,  CHENG, Yana ,  CAO, Yong ,  DIEHL, Daniel Lee ,  GUGGILLA, Srinivas ,  WANG, Rongjun ,  TANG, Xianmin

IPC: H01L21/02 ,  H01L21/203 ,  H01L21/205

CPC classification number: H01L21/0234 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02266

Abstract: In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness.

Abstract translation: 在一些实施例中，处理设置在物理气相沉积处理室中的衬底支架顶上的衬底的方法包括：（a）通过物理气相沉积工艺在介质的第一表面顶部沉积介电层至第一厚度; （b）向所述物理气相沉积处理室的处理区域提供第一等离子体形成气体，其中所述第一等离子体形成气体包括氢而不是碳; （c）向所述衬底支撑件提供第一量的偏置功率以从所述物理气相沉积处理室的处理区域内的所述第一等离子体形成气体形成第一等离子体; （d）将介电层暴露于第一等离子体; 和（e）重复（a） - （d）将电介质膜沉积到最终厚度。

公开(公告)号：WO2017062355A2

公开(公告)日：2017-04-13

申请号：PCT/US2016/055317

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： KESAPRAGADA, Sree Rangasai V. ,  MORAES, Kevin ,  GUGGILLA, Srinivas ,  REN, He ,  NAIK, Mehul ,  THOMPSON, David ,  YE, Weifeng ,  CHENG, Yana ,  CAO, Yong ,  TANG, Xianmin ,  MA, Paul F. ,  PADHI, Deenesh

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

Abstract translation: 在一些实施例中，形成互连结构的方法包括在具有一个或多个暴露的金属表面和一个或多个暴露的电介质表面的衬底上选择性地沉积阻挡层，其中阻挡层的厚度在一个或多个暴露的金属表面 大于在一个或多个暴露的电介质表面上方的阻挡层的厚度。 在一些实施例中，形成互连结构的方法包括通过物理气相沉积工艺沉积包含在基板顶上的铝的蚀刻停止层; 以及通过化学气相沉积工艺在所述蚀刻停止层的顶部沉积阻挡层，其中，在将所述蚀刻停止层沉积到化学气相沉积室之后，所述衬底从物理气相沉积室转移而不将所述衬底暴露于大气。

公开(公告)号：WO2019125900A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/065412

申请日：2018-12-13

Applicant: APPLIED MATERIALS, INC.

Inventor： NGUYEN, Thanh X. ,  JANSEN, Alexander ,  CHENG, Yana ,  SCHMIEDING, Randal ,  CAO, Yong ,  TANG, Xianmin ,  JOHANSON, William

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/683 ,  H01L21/02

Abstract: A movable substrate support with a top surface for holding a substrate, when present, is used in conjunction with a cover ring that is stationary to adjust for a shadow effect to control substrate edge uniformity during deposition processes. The cover ring is held stationary by an electrically isolated spacer that engages with a grounded shield in the process volume of a semiconductor process chamber. A controller adjusts the substrate support in response to deposition material on a top surface of the cover ring to maintain the shadow effect and substrate edge uniformity.

公开(公告)号：WO2017062355A3

公开(公告)日：2017-04-13

申请号：PCT/US2016/055317

申请日：2016-10-04

Applicant: APPLIED MATERIALS, INC.

Inventor： KESAPRAGADA, Sree Rangasai V. ,  MORAES, Kevin ,  GUGGILLA, Srinivas ,  REN, He ,  NAIK, Mehul ,  THOMPSON, David ,  YE, Weifeng ,  CHENG, Yana ,  CAO, Yong ,  TANG, Xianmin ,  MA, Paul F. ,  PADHI, Deenesh

IPC: H01L21/768

Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：WO2017004075A1

公开(公告)日：2017-01-05

申请号：PCT/US2016/039881

申请日：2016-06-28

Applicant: APPLIED MATERIALS, INC.

Inventor： REN, He ,  NAIK, Mehul B. ,  CAO, Yong ,  CHENG, Yana ,  YE, Weifeng

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

Abstract translation: 本公开提供了形成在衬底上的互连和用于在衬底上形成互连的方法。 在一个实施例中，用于在衬底上形成互连的方法包括在衬底上沉积阻挡层，在阻挡层上沉积过渡层，以及在过渡层上沉积蚀刻停止层，其中过渡层共享共同 元件，并且其中所述过渡层与所述蚀刻停止层共享公共元件。

公开(公告)号：WO2016130787A1

公开(公告)日：2016-08-18

申请号：PCT/US2016/017523

申请日：2016-02-11

Applicant: APPLIED MATERIALS, INC.

Inventor： CHENG, Yana ,  CAO, Yong ,  GUGGILLA, Srinivas ,  KESAPRAGADA, Sree Rangasai ,  TANG, Xianmin ,  PADHI, Deenesh

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  C23C14/0036 ,  C23C14/0676 ,  C23C14/352 ,  H01J37/32504 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/02145 ,  H01L21/02266 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAION) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAION) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAION) layer to expose the first conductive material.

Abstract translation: 本文提供互连结构和形成这种互连结构的方法。 在一些实施例中，形成互连的方法包括：在衬底的第一层的顶部沉积硅 - 铝氮氧化物（SiAION）层，其中第一层包括填充有第一导电材料的第一特征; 在硅 - 铝氮氧化物（SiAION）层上沉积介电层; 以及在介电层和硅 - 铝氧氮化物（SiAION）层中形成第二特征以露出第一导电材料。

公开(公告)号：WO2015134118A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/011453

申请日：2015-01-14

Applicant: APPLIED MATERIALS, INC.

Inventor： REN, He ,  NAIK, Mehul, B. ,  CAO, Yong ,  KESAPRAGADA, Sree Rangasai, V. ,  SHEK, Mei-yee ,  CHENG, Yana

IPC: H01L21/768

CPC classification number: H01L21/76841 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/321 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849

Abstract: Methods for forming a passivation protection structure on a metal line layer formed in an insulating material in an interconnection structure are provided. In one embodiment, a method for forming passivation protection on a metal line in an interconnection structure for semiconductor devices includes selectively forming a metal capping layer on a metal line bounded by a dielectric bulk insulating layer in an interconnection structure formed on a substrate in a processing chamber incorporated in a multi-chamber processing system, in-situ forming a barrier layer on the substrate in the processing chamber; wherein the barrier layer is a metal dielectric layer, and forming a dielectric capping layer on the barrier layer in the multi-chamber processing system.

Abstract translation: 提供了在形成在互连结构中的绝缘材料中的金属线层上形成钝化保护结构的方法。 在一个实施例中，用于在半导体器件的互连结构中的金属线上形成钝化保护的方法包括在处理中形成在基板上的互连结构中的介电体绝缘层界定的金属线上选择性地形成金属覆盖层 结合在多腔室处理系统中，在处理室中的基底上原位形成阻挡层; 其中所述阻挡层是金属介电层，并且在所述多室处理系统中的阻挡层上形成电介质覆盖层。

公开(公告)号：WO2015119760A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/011714

申请日：2015-01-16

Applicant: APPLIED MATERIALS, INC.

Inventor： REN, He ,  NAIK, Mehul B. ,  CAO, Yong ,  SHEK, Mei-yee ,  CHENG, Yana ,  KESAPRAGADA, Sree Rangasai V.

IPC: H01L21/3205 ,  H01L21/28

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

Abstract translation: 描述了用于半导体器件的互连结构及其制造方法。 该方法包括将基板定位在真空处理室中。 衬底具有暴露的铜表面和暴露的低k电介质表面。 在铜表面上形成金属层，但不在低k电介质表面上。 在金属层和低k电介质层上形成金属基介电层。