公开(公告)号：WO2017123552A1

公开(公告)日：2017-07-20

申请号：PCT/US2017/012872

申请日：2017-01-10

Applicant: APPLIED MATERIALS, INC.

Inventor： HSU, Hao-Chien ,  YIM, Dong-Kil ,  WON, Tae Kyung ,  ZHANG, Xuena ,  SUNG, Won Ho ,  LIM, Rodney Shunleong

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/02631 ,  H01L21/02664 ,  H01L29/7869

Abstract: Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.

Abstract translation: 本公开的实施例总体上涉及用于形成具有金属氧化物层的TFT的方法。 该方法可以包括形成金属氧化物层并用含氟气体或等离子体处理金属氧化物层。 金属氧化物层的氟处理有助于填充金属氧化物沟道层中的氧空位，导致更稳定的TFT并防止TFT中的负阈值电压。

公开(公告)号：WO2018108239A1

公开(公告)日：2018-06-21

申请号：PCT/EP2016/080662

申请日：2016-12-12

Applicant: APPLIED MATERIALS, INC. ,  MUELLER, Bernhard G. ,  ZHANG, Xuena ,  NUNAN, Peter ,  VIRDI, Kulpreet Singh

Inventor： MUELLER, Bernhard G. ,  ZHANG, Xuena ,  NUNAN, Peter ,  VIRDI, Kulpreet Singh

IPC: H01J37/28 ,  H01J37/22 ,  G06T7/55

Abstract: A method for inspecting a substrate is described. The method includes providing the substrate being a large area substrate in a vacuum chamber, wherein the substrate has a thin-film with a grain structure deposited on the substrate; generating a primary charged particle beam with an imaging charged particle beam microscope, wherein the primary charged particle beam impinges on the substrate in the vacuum chamber; and generating one or more images from signal particles released from the substrate upon impingement of the primary charged particle beam, wherein the one or more images are topographic images.

公开(公告)号：WO2018236651A1

公开(公告)日：2018-12-27

申请号：PCT/US2018/037396

申请日：2018-06-13

Applicant: APPLIED MATERIALS, INC.

Inventor： NUNAN, Peter ,  ZHANG, Xuena

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/311 ,  G03F7/20

Abstract: Methods for forming flat panel displays, and more particularly, methods for forming high pixel density flat panel displays are provided. A method of etching can include depositing a copper layer on a substrate, depositing a hard mask on the copper layer, patterning the hard mask to expose a first portion of the copper layer, and removing the exposed portion of the copper to form an interconnect. The removing the exposed portion of the copper includes dry etching the exposed portion of the copper and exposing the exposed portion of the copper to UV radiation.

公开(公告)号：WO2017136141A1

公开(公告)日：2017-08-10

申请号：PCT/US2017/013953

申请日：2017-01-18

Applicant: APPLIED MATERIALS, INC.

Inventor： ZHANG, Xuena ,  YIM, Dong-kil ,  DAI, Wenqing ,  YOU, Harvey ,  WON, Tae Kyung ,  YANG, Hsiao-Lin ,  LIN, Wan-Yu ,  TSAI, Yun-chu

IPC: G02F1/1368 ,  G02F1/1343

CPC classification number: H01L29/4908 ,  G02F1/136213 ,  G02F1/1368 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L28/40 ,  H01L28/60 ,  H01L2227/323

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Abstract translation: 本公开的实施例通常提供形成具有高电容和低漏电的电容器以及用于薄膜晶体管（TFT）应用的良好接口控制的方法。 在一个实施例中，薄膜晶体管结构包括形成在薄膜晶体管器件中的电容器。 该电容器还包括设置在衬底上的公共电极，形成在公共电极上的电介质层和形成在电介质层上的像素电极。 界面保护层形成于公共电极与介电层之间或介电层与像素电极之间。 在薄膜晶体管结构中也可以使用由高k材料制成的栅绝缘层。

公开(公告)号：WO2017007582A1

公开(公告)日：2017-01-12

申请号：PCT/US2016/037618

申请日：2016-06-15

Applicant: APPLIED MATERIALS, INC.

Inventor： CHOI, Soo Young ,  WON, Tae Kyung ,  YIM, Dong-Kil ,  WHITE, John M. ,  CUI, Yi ,  ZHANG, Xuena

IPC: H01L29/786 ,  H01L27/32 ,  G02F1/136

CPC classification number: H01L27/1248 ,  H01L27/3262

Abstract: Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.

Abstract translation: 本公开的实施例一般涉及在液晶显示器（LCD）和有机发光二极管（OLED）显示器中使用低温多晶硅（LTPS）薄膜晶体管的方法和装置。