公开(公告)号：WO2012170160A1

公开(公告)日：2012-12-13

申请号：PCT/US2012/038075

申请日：2012-05-16

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt

IPC: H01L21/36 ,  H01L21/44 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/428 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

Abstract translation: 在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括：提供栅极，栅极电介质，具有带隙的高载流子浓度金属氧化物半导体有源层和间隔开的薄/弱金属氧化物半导体有源层 薄膜晶体管配置。 间隔开的源极/漏极金属触点限定有源层中的沟道区。 在沟道区域附近提供氧化环境，并且在氧化环境中加热栅极和沟道区域以降低沟道区域中的载流子浓度。 或者或另外每个源极/漏极触点包括位于金属氧化物半导体有源层上的非常薄的低功函数金属层，并且高功函数金属的阻挡层位于低功函数金属上。

公开(公告)号：WO2012057903A1

公开(公告)日：2012-05-03

申请号：PCT/US2011/047768

申请日：2011-08-15

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  FOONG, Fatt ,  YU, Gang

Inventor： SHIEH, Chan-long ,  FOONG, Fatt ,  YU, Gang

IPC: H01L29/788

CPC classification number: H01L29/7869 ,  H01L29/78696

Abstract: A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of low trap density material is sandwiched between the active layer of metal oxide and the layer of gate dielectric. The layer of low trap density material has a major surface parallel and in contact with a major surface of the active layer of metal oxide to form a low trap density interface with the active layer of metal oxide. A second layer of low trap density material can optionally be placed in contact with the opposed major surface of the active layer of metal oxide so that a low trap density interface is formed with both surfaces of the active layer of metal oxide.

Abstract translation: 一种金属氧化物半导体器件，包括金属氧化物的有源层，栅极电介质层和低陷阱密度材料层。 低陷阱密度材料层夹在金属氧化物的有源层和栅极电介质层之间。 低陷阱密度材料层的主表面平行并与金属氧化物的有源层的主表面接触，以形成与金属氧化物的有源层的低陷阱密度界面。 可以可选地将第二层低陷阱密度材料放置成与金属氧化物的有源层的相对的主表面接触，使得与金属氧化物的活性层的两个表面形成低陷阱密度界面。

公开(公告)号：WO2011022144A1

公开(公告)日：2011-02-24

申请号：PCT/US2010/042385

申请日：2010-07-19

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  YU, Gang

Inventor： SHIEH, Chan-long ,  YU, Gang

IPC: H01L51/50

CPC classification number: H01L27/3244 ,  H01L27/3204 ,  H01L27/3246

Abstract: An active matrix organic light emitting display includes a plurality of pixels with each pixel including at least one organic light emitting diode circuit. Each diode circuit producing a predetermined amount of light Im in response to power W applied to the circuit and including n organic light emitting diodes cascaded in series so as to increase voltage dropped across the cascaded diodes by the factor of n, where n is an integer greater than one. Each diode of the n organic light emitting diodes produces approximately 1/n of the predetermined amount of light Im so as to reduce current flowing in the diodes by 1/n. The organic light emitting diode circuit of each pixel includes a thin film transistor current driver with the cascaded diodes connected in the source/drain circuit so the current driver provides the current flowing in the diodes.

Abstract translation: 有源矩阵有机发光显示器包括多个像素，每个像素包括至少一个有机发光二极管电路。 每个二极管电路响应于施加到电路的功率W产生预定量的光Im，并且包括串联级联的n个有机发光二极管，以便增加跨越级联二极管的电压以n为因子，其中n是整数 大于一。 n个有机发光二极管的每个二极管产生大约1 / n个预定量的光Im，以便将在二极管中流动的电流减少1 / n。 每个像素的有机发光二极管电路包括薄膜晶体管电流驱动器，其中级联二极管连接在源极/漏极电路中，因此电流驱动器提供流过二极管的电流。

公开(公告)号：WO2012115745A1

公开(公告)日：2012-08-30

申请号：PCT/US2012/022867

申请日：2012-01-27

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  YU, Gang

Inventor： SHIEH, Chan-long ,  YU, Gang

IPC: H01L29/10

CPC classification number: G09G3/3225 ,  G09G2310/063 ,  G09G2320/0204

Abstract: A method of driving a display device includes providing an array of pixels including rows and columns of pixels, each pixel including a switching/driving transistor circuit and at least one light emitting device. Each row of pixels has a scan line and each column of pixels has a data line. The method further includes defining a frame period during which each pixel in the array of pixels is addressed and dividing the frame period into a write subframe, a display subframe, and a rest subframe. A scan pulse is supplied to each scan line, a data signal to each data line and the light emitting devices are disabled during the write subframe. The light emitting devices are enabled during the display subframe and the switching/driving transistor circuits are disabled. A rest pulse is supplied to all scan lines and the light emitting devices are disabled during the rest subframe.

Abstract translation: 一种驱动显示装置的方法包括提供包括行和列的像素的像素阵列，每个像素包括开关/驱动晶体管电路和至少一个发光器件。 每行像素具有扫描线，并且每列像素具有数据线。 该方法还包括定义帧期间，在该帧周期期间，像素阵列中的每个像素被寻址并且将帧周期划分为写子帧，显示子帧和剩余子帧。 向每条扫描线提供扫描脉冲，在写入子帧期间，对每个数据线的数据信号和发光器件禁用。 发光器件在显示子帧期间被使能，并且开关/驱动晶体管电路被禁止。 向所有扫描线提供静止脉冲，并且在其余子帧期间禁用发光装置。

公开(公告)号：WO2010028269A2

公开(公告)日：2010-03-11

申请号：PCT/US2009/056079

申请日：2009-09-04

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  YU, Gang

Inventor： SHIEH, Chan-long ,  YU, Gang

IPC: H01L29/24 ,  H01L21/20

CPC classification number: H01L29/04 ,  H01L21/00 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/16 ,  H01L21/28556 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78693 ,  H01L51/5012

Abstract: A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

Abstract translation: 薄膜半导体器件具有包括非晶半导体离子金属氧化物和非晶绝缘共价金属氧化物的混合物的半导体层。 一对端子被定位成与半导体层连通并且限定导电通道，并且栅极端子被定位成与导电通道连通并进一步定位成控制通道的导通。 本发明还包括在沉积过程中沉积包括使用氮气的混合物的方法，以控制所得半导体层中的载流子浓度。

公开(公告)号：WO2014189681A2

公开(公告)日：2014-11-27

申请号：PCT/US2014/037191

申请日：2014-05-07

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt ,  MUSOLF, Juergen

IPC: H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/02063 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2021/775

Abstract: A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ . The layer of amorphous metal oxide has a mobility above 40 cm 2 /Vs and a carrier concentration in a range of approximately 10 18 cm -3 to approximately 5xl0 19 cm -3 . Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

Abstract translation: 制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。 通过溅射将载流子传输结构沉积在栅极介电层上。 载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。 无定形金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。 源极/漏极触点位于保护层上并与其电接触。

公开(公告)号：WO2013181166A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/042926

申请日：2013-05-28

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt ,  LEE, Liu-chung

IPC: G02F1/1343

CPC classification number: G02F1/134363 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1225 ,  H01L27/1288

Abstract: A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

Abstract translation: 制造具有减小的掩模操作的TFT和IPS的方法包括在栅极和周围的衬底表面上的衬底，栅极，栅极电介质层和栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 在沟道保护层和暴露的半导体金属氧化物的一部分上形成S / D金属层以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层，以限定覆盖第一电极的第二IPS电极。

公开(公告)号：WO2016025731A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/045083

申请日：2015-08-13

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang

IPC: H01L27/146

CPC classification number: H01L27/14663 ,  H01L27/14612 ,  H01L27/14658 ,  H01L27/14692 ,  H01L27/308 ,  H01L51/4293

Abstract: A method of fabricating an X-ray imager including the steps of forming an etch stop layer on a glass substrate and depositing a stack of semiconductor layers on the etch stop layer to form a sensor plane. Separating the stack into an array of PIN photodiodes. Depositing a layer of insulating material on the array to form a planarized surface and forming vias through the insulating layer into communication with an upper surface of each photodiode and forming metal contacts on the planarized surface through the vias in contact with each photodiode. Fabricating an array of MOTFTs in an active pixel sensor configuration backplane on the planarized surface and in electrical communication with the contacts, to provide a sensor plane/MOTFT backplane interconnected combination. Attaching a flexible support carrier to the MOTFT backplane and removing the glass substrate. A scintillator is then laminated on the array of photodiodes.

Abstract translation: 一种制造X射线成像仪的方法，包括以下步骤：在玻璃衬底上形成蚀刻停止层，并在蚀刻停止层上淀积一叠半导体层以形成传感器平面。 将堆叠分成PIN光电二极管阵列。 在阵列上沉积绝缘材料层以形成平坦化表面，并且通过绝缘层形成通孔，与每个光电二极管的上表面连通，并通过与每个光电二极管接触的通孔在平坦化表面上形成金属触点。 在平坦化表面上的有源像素传感器配置底板中和与触点电连通的MOTFT阵列制造，以提供传感器平面/ MOTFT背板互连的组合。 将柔性支撑载体安装到MOTFT背板上，并拆下玻璃基板。 然后将闪烁体层压在光电二极管阵列上。

公开(公告)号：WO2008091456A1

公开(公告)日：2008-07-31

申请号：PCT/US2007/087608

申请日：2007-12-14

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long

IPC: G02F3/02

CPC classification number: G09G3/344 ,  G02F1/157 ,  G02F1/167 ,  G09G2300/0426 ,  G09G2300/08

Abstract: Reconfigurable color signage includes an array of light valves each having memory. An active matrix including a plurality of conductive select and data lines is positioned on one side of the array. Each light valve is electrically coupled to be separately addressable by a unique combination of select and data line. The active matrix has a write mode in which signals are supplied to each light valve to provide a selected light transmittance and a display mode in which the memory of each light valve retains the selected transmittance after the signals of the write mode have been removed. A backlight is positioned to direct light in a light path through the array and a color filter is positioned in the light path to define a plurality of pixels, including one red, green, and blue filter for each pixel, and each positioned to be associated with a separate light valve.

Abstract translation: 可重构颜色标志包括每个具有存储器的光阀阵列。 包括多个导电选择和数据线的有源矩阵位于阵列的一侧。 每个光阀电耦合以通过选择和数据线的独特组合单独寻址。 有源矩阵具有写入模式，其中向每个光阀提供信号以提供选择的光透射率和显示模式，其中每个光阀的存储器在写入模式的信号已被去除之后保持所选择的透射率。 背光被定位成在通过阵列的光路中引导光，并且滤光器定位在光路中以限定多个像素，包括用于每个像素的一个红色，绿色和蓝色滤光器，并且每个像素定位成相关联 带有独立的光阀。

公开(公告)号：WO2018034982A1

公开(公告)日：2018-02-22

申请号：PCT/US2017/046500

申请日：2017-08-11

Applicant: CBRITE INC.

Inventor： GUNNING, Kerry ,  ACKLEY, Donald ,  SHIEH, Chan-long

IPC: C12Q1/68 ,  C12M1/34

CPC classification number: G01N21/6428 ,  C12Q1/6869 ,  G01N27/4145 ,  G01N2021/6439 ,  G01N2201/062 ,  C12Q2563/107 ,  C12Q2565/607

Abstract: Apparatus for fluorescent and ion sensing of DNA nucleotide incorporation events including DNA nucleotide incorporation structure designed to have sequencing primers bonded to a surface for the incorporation of DNA nucleotides thereon. At least some of the DNA nucleotides having a fluorescent label. A photodiode positioned adjacent the incorporation structure and an illumination device positioned adjacent the DNA nucleotide incorporation structure to illuminate DNA nucleotides incorporated onto the sequencing primers. The illumination device exciting the fluorescent labels when incorporation occurs and the photodiode positioned to sense the excited fluorescent labels. Ion sensing apparatus positioned adjacent the DNA nucleotide incorporation structure including a metal oxide thin film transistor with a gate electrically coupled to receive an electrical signal indicative of ion emissions produced by the DNA nucleotide incorporated onto DNA target fragments or sequencing primers.

Abstract translation: 用于DNA核苷酸掺入事件的荧光和离子感应的装置，包括DNA核苷酸掺入结构，其被设计为具有结合到表面以将DNA核苷酸掺入其上的测序引物。 至少一些具有荧光标记的DNA核苷酸。 位于掺入结构附近的光电二极管和位于DNA核苷酸掺入结构附近的照明装置，以照射掺入到测序引物中的DNA核苷酸。 照明装置在结合时激发荧光标签并且光电二极管定位为感测激发的荧光标签。 离子感测装置位于DNA核苷酸掺入结构附近，包括金属氧化物薄膜晶体管，其栅极电耦合以接收指示由掺入DNA靶片段或测序引物的DNA核苷酸产生的离子发射的电信号。