公开(公告)号：WO2014150791A3

公开(公告)日：2014-11-13

申请号：PCT/US2014024245

申请日：2014-03-12

Applicant: QUALCOMM INC ,  UNIV YONSEI IACF

Inventor： JUNG SEONG-OOK ,  NA TAEHUI ,  KIM JISU ,  KANG SEUNG H ,  KIM JUNG PILL

IPC: G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2207/002

Abstract: A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage.

Abstract translation: 一种方法包括感测数据单元的状态以产生数据电压。 数据单元的状态对应于数据单元的基于可编程电阻的存储元件的状态。 该方法还包括感测参考单元的状态以产生参考电压。 通过公共感测路径来检测数据单元的状态和参考单元的状态。 该方法还包括基于数据电压和参考电压来确定数据单元的逻辑值。

公开(公告)号：WO2013071176A3

公开(公告)日：2013-10-17

申请号：PCT/US2012064536

申请日：2012-11-09

Applicant: QUALCOMM INC

Inventor： LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  KIM JUNG PILL ,  HSU WAH NAM ,  KIM TAEHYUN ,  LEE KANGHO

IPC: G11C11/16 ,  H01L29/82

CPC classification number: G11C11/161 ,  G11C8/16 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08

Abstract: A two-transistor one-MTJ (2T1MTJ) three port structure includes two separate pin layer structures coupled to one free layer structure. The pin layer structures may include an anti-ferromagnetic layer (AFM) layer coupled to a pin layer. The free layer structure includes free layer coupled to a barrier layer and a cap layer. The free layer structure may include a thin barrier layer coupled to each of the pin layer stacks. The three port MTJ structure provides separate write and read paths which improve read sensing margin without increasing write voltage or current. The three port MTJ structure may be fabricated with a simple two step MTJ etch process.

Abstract translation: 双晶体管单MTJ（2T1MTJ）三端口结构包括耦合到一个自由层结构的两个分离的引脚层结构。 引脚层结构可以包括耦合到引脚层的反铁磁层（AFM）层。 自由层结构包括耦合到阻挡层和帽层的自由层。 自由层结构可以包括耦合到每个引脚层堆叠的薄阻挡层。 三端口MTJ结构提供独立的写入和读取路径，这些路径在不增加写入电压或电流的情况下提高读取感测裕度。 三端口MTJ结构可以用简单的两步MTJ刻蚀工艺制造。

公开(公告)号：WO2012019135A3

公开(公告)日：2012-03-29

申请号：PCT/US2011046811

申请日：2011-08-05

Applicant: QUALCOMM INC ,  LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

Inventor： LI XIA ,  ZHU XIAOCHUN ,  KANG SEUNG H

IPC: H01L27/22 ,  B82Y25/00 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  B82Y10/00 ,  G11C11/161 ,  H01L27/228 ,  H01L43/08

Abstract: A semiconductor device includes a magnetic tunnel junction (MTJ) storage element configured to be disposed in a common interlayer metal dielectric (IMD) layer with a logic element. Cap layers separate the common IMD layer from a top and bottom IMD layer. Top and bottom electrodes are coupled to the MTJ storage element. Metal connections to the electrodes are formed in the top and bottom IMD layers respectively through vias in the separating cap layers. Alternatively, the separating cap layers are recessed and the bottom electrodes are embedded, such that direct contact to metal connections in the bottom IMD layer is established. Metal connections to the top electrode in the common IMD layer are enabled by isolating the metal connections from the MTJ storage elements with metal islands and isolating caps.

Abstract translation: 一种半导体器件包括被配置为设置在具有逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）存储元件。 盖层将普通IMD层与顶部和底部IMD层分开。 顶部和底部电极连接到MTJ存储元件。 与电极的金属连接分别通过分离帽层中的通孔形成在顶部和底部IMD层中。 可选地，分离盖层凹入并且底部电极被嵌入，从而建立与底部IMD层中的金属连接的直接接触。 通过将金属连接与MTJ存储元件与金属岛和隔离帽隔离，可以实现与公共IMD层中的顶部电极的金属连接。

公开(公告)号：WO2010120918A3

公开(公告)日：2011-01-20

申请号：PCT/US2010031080

申请日：2010-04-14

Applicant: QUALCOMM INC ,  ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

Inventor： ZHU XIAOCHUN ,  NOWAK MATTHEW ,  LI XIA ,  KANG SEUNG H

IPC: H01L27/115 ,  G11B5/39 ,  G11C11/15

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.

Abstract translation: 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。

公开(公告)号：WO2010101860A3

公开(公告)日：2010-11-11

申请号：PCT/US2010025834

申请日：2010-03-02

Applicant: QUALCOMM INC ,  LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

Inventor： LEE KANGHO ,  KANG SEUNG H ,  ZHU XIAOCHUN

IPC: G11C11/16

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: Systems and methods to reduce source loading effects in STT-MRAM are disclosed. In a particular embodiment, a method includes determining a switching current ratio of a magnetic tunnel junction (MTJ) structure that enables stable operation of a memory cell. The memory cell includes the MTJ structure serially coupled to an access transistor. The method also includes modifying an offset magnetic field that is incident to a free layer of the MTJ structure. The modified offset magnetic field causes the MTJ structure to exhibit the switching current ratio.

Abstract translation: 公开了减少STT-MRAM中的源负载效应的系统和方法。 在特定实施例中，一种方法包括确定使得能够稳定地操作存储器单元的磁性隧道结（MTJ）结构的开关电流比。 存储单元包括串行耦合到存取晶体管的MTJ结构。 该方法还包括修改入射到MTJ结构的自由层的偏移磁场。 改进的偏移磁场使MTJ结构呈现开关电流比。

公开(公告)号：WO2013119846A3

公开(公告)日：2013-12-05

申请号：PCT/US2013025191

申请日：2013-02-07

Applicant: QUALCOMM INC

Inventor： LI XIA ,  WU WENQING ,  KIM JUNG PILL ,  ZHU XIAOCHUN ,  KANG SEUNG H ,  MADALA RAGHU SAGAR ,  YUEN KENDRICK H

IPC: G11C11/16 ,  G11C11/56 ,  H01L27/22

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C2211/5615 ,  G11C2211/562 ,  G11C2211/5633 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08

Abstract: A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an antiferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the antiferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.

Abstract translation: 多自由层磁隧道结（MTJ）单元包括底部电极层，底部电极层上的反铁磁层，反铁磁层上的固定磁化层和固定磁化层上的阻挡层。 第一自由磁化层位于阻挡层的第一区域上，盖层位于第一自由磁化层上。 自由磁化层位于阻挡层的第二区域上，与第一区域横向偏移，并且封盖层位于第二自由磁化层上。 可选地，电流开关在未建立包括第二自由磁化层的读取电流路径的同时建立包括第一自由磁化层的读取电流路径。 可选地，电流开关建立包括第一和第二自由磁化层的读取电流路径。

公开(公告)号：WO2012015754A2

公开(公告)日：2012-02-02

申请号：PCT/US2011045222

申请日：2011-07-25

Applicant: QUALCOMM INC ,  JUNG SEONG-OOK ,  RYU KYUNGHO ,  KIM JISU ,  KIM JUNG PILL ,  KANG SEUNG H

Inventor： JUNG SEONG-OOK ,  RYU KYUNGHO ,  KIM JISU ,  KIM JUNG PILL ,  KANG SEUNG H

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.

Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括第一基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过第一基于电阻的存储元件的电流。 感测电路还可以包括n型金属氧化物半导体（NMOS）晶体管，以向第一电流路径提供降压电源电压。

公开(公告)号：WO2011066579A3

公开(公告)日：2011-07-21

申请号：PCT/US2010058445

申请日：2010-11-30

Applicant: QUALCOMM INC ,  LI XIA ,  KANG SEUNG H

Inventor： LI XIA ,  KANG SEUNG H

IPC: H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/307 ,  H01L27/222 ,  H01L43/08

Abstract: Disclosed is an electronic device manufacturing process including depositing a bottom electrode layer (711). Then an electronic device (721) is fabricated on the bottom electrode layer. Patterning of the bottom electrode layer is performed after fabricating the electronic device and in a separate process from patterning a top electrode. A first dielectric layer (740) is then deposited on the electronic device and the bottom electrode layer followed by a top electrode layer (751). The top electrode is then patterned in a separate process from the bottom electrode. Separately patterning the top and bottom electrodes improves yields by reducing voids in the dielectric material between electronic devices. One electronic device the manufacturing process is well -suited for is magnetic tunnel junctions (MTJs).

Abstract translation: 公开了一种电子器件制造方法，包括沉积底部电极层（711）。 然后在底部电极层上制造电子器件（721）。 底部电极层的图案化是在制造电子器件之后并且在单独的工艺中对图案化顶部电极进行的。 然后，第一电介质层（740）沉积在电子器件上，底部电极层后面是顶部电极层（751）。 然后在与底部电极分离的工艺中对顶部电极进行图案化。 单独图案化顶部和底部电极通过减少电子器件之间的电介质材料中的空隙来提高产率。 磁性隧道结（MTJ）是制造工艺很好的一种电子器件。

公开(公告)号：WO2009052371A3

公开(公告)日：2009-06-11

申请号：PCT/US2008080300

申请日：2008-10-17

Applicant: QUALCOMM INC ,  YOON SEI SEUNG ,  KANG SEUNG H

Inventor： YOON SEI SEUNG ,  KANG SEUNG H

IPC: G11C11/16

CPC classification number: G11C11/1693 ,  G11C11/1673

Abstract: Systems, circuits and methods for read operations in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. A plurality of bit cells, each coupled to one of a plurality of bit lines, word lines and source lines are provided. A plurality of precharge transistors corresponding to one of the plurality of bit lines are configured to discharge the bit lines to ground prior to a read operation.

Abstract translation: 公开了用于旋转转矩磁阻随机存取存储器（STT-MRAM）中读操作的系统，电路和方法。 提供了多个位单元，每个位单元耦合到多个位线，字线和源极线之一。 对应于多个位线之一的多个预充电晶体管被配置为在读取操作之前将位线放电到地。

公开(公告)号：WO2013071254A3

公开(公告)日：2013-11-14

申请号：PCT/US2012064703

申请日：2012-11-12

Applicant: QUALCOMM INC

Inventor： ZHU XIAOCHUN ,  LI SEAN ,  WU WENQING ,  KIM JUNG PILL ,  KANG SEUNG H

IPC: G11C11/16 ,  G11C5/14

CPC classification number: G11C11/16 ,  G11C5/147 ,  G11C11/1673

Abstract: A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.

Abstract translation: 建立参考电平的方法包括提供从第一节点到第二节点的第一和第二非重叠路径，在第一路径中提供第一和第二参考磁随机存取存储器（MRAM）元件，提供第三和第四参考MRAM元件 在所述第二路径中，测量指示所述第一节点和所述第二节点之间的电阻的第一值，并且至少部分地基于所述测量值来设置所述参考电平。 还有一个相关的参考电路。