公开(公告)号：WO2016085569A1

公开(公告)日：2016-06-02

申请号：PCT/US2015/053179

申请日：2015-09-30

申请人： SANDISK TECHNOLOGIES, INC.

发明人： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka Krishna ,  KOKA, Sateesh ,  LEE, Yao-Sheng ,  MATAMIS, George

IPC分类号： H01L27/115

CPC分类号： H01L27/11556 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28556 ,  H01L21/28568 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/7883

摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.

摘要翻译： 一种制造单片三维NAND串的方法，包括在所述基板的主表面上形成绝缘的第一材料和不同于所述第一材料的牺牲第二材料的交替层的堆叠，在所述堆叠中形成前侧开口，至少形成 在前侧开口中的一个电荷存储区域，并且在前侧开口中的至少一个电荷存储区域上形成隧道电介质层。 该方法还包括在前侧开口的隧道电介质层之上形成半导体沟道，在堆叠中形成背面开口，并选择性地移除第二材料层的至少一部分，以在相邻的第一材料层之间形成背面凹槽。 该方法还包括在后侧凹槽中形成导电蛤形成核衬砌区域，并通过相应的导电蛤形成核区域中的背侧开口选择性地形成钌控制栅电极。

公开(公告)号：WO2015002867A1

公开(公告)日：2015-01-08

申请号：PCT/US2014/044833

申请日：2014-06-30

申请人： SANDISK TECHNOLOGIES, INC.

发明人： MAKALA, Raghuveer S. ,  ALSMEIER, Johann ,  LEE, Yao-Sheng ,  TERAHARA, Masanori ,  WATATANI, Hirofumi ,  PACHAMUTHU, Jayavel

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1157

摘要： A method of making a semiconductor device including forming a sacrificial feature over a substrate, forming a plurality of etch through regions having an etch through material and an etch stop region having an etch stop material over the sacrificial feature, forming a stack of alternating layers of a first material and a second material over the plurality of the etch through regions and the plurality of the etch stop regions, etching the stack to form a plurality of openings through the stack and through the etch through regions to expose the sacrificial feature, such that the etch through material is etched preferentially compared to the first and the second materials of the stack, removing the sacrificial feature through the plurality of openings and etching the stack to form a slit trench up to or only partially through the etch stop region, such that the first and the second materials of the stack are etched preferentially compared to the etch stop material.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成牺牲特征，通过具有蚀刻穿过材料的区域和在所述牺牲特征上具有蚀刻停止材料的蚀刻停止区域形成多个蚀刻，形成交替层 在所述多个蚀刻通过区域和所述多个蚀刻停止区域之上的第一材料和第二材料，蚀刻所述堆叠以形成穿过所述堆叠并穿过所述蚀刻通过区域以暴露所述牺牲特征的多个开口，使得 与叠层的第一和第二材料相比，优先蚀刻蚀刻材料，通过多个开口去除牺牲特征并蚀刻叠层以形成直到或仅部分地穿过蚀刻停止区域的狭缝沟槽，使得 与蚀刻停止材料相比，优先蚀刻叠层的第一和第二材料。

公开(公告)号：WO2016085572A1

公开(公告)日：2016-06-02

申请号：PCT/US2015/053829

申请日：2015-10-02

申请人： SANDISK TECHNOLOGIES, INC.

发明人： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  MATAMIS, George

IPC分类号： H01L27/115

CPC分类号： H01L29/1054 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile- stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress- generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.

摘要翻译： 存储器膜和半导体沟道形成在每个存储器开口内，其延伸穿过包括交替的多个绝缘体层和牺牲材料层的堆叠。 在通过去除对绝缘体层选择性的牺牲材料层形成后侧凹槽之后，在背面凹槽中形成导电层。 每个导电层包括产生拉伸应力的金属材料和产生压应力的金属材料的组合。 拉伸应力产生金属材料可以是钌，并且压应力产生金属材料可以是钨。 可以进行退火以提供产生压应力的金属材料和拉伸应力产生金属材料的合金。

公开(公告)号：WO2016032838A2

公开(公告)日：2016-03-03

申请号：PCT/US2015/046035

申请日：2015-08-20

申请人： SANDISK TECHNOLOGIES INC.

发明人： MAKALA, Raghuveer S. ,  ZHANG, Yanli ,  SHARANGPANI, Rahul ,  LEE, Yao-Sheng ,  KANAKAMEDALA, Senaka Krishna ,  MATAMIS, George ,  ALSMEIER, Johann

IPC分类号： H01L27/115

CPC分类号： H01L29/66825 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833

摘要： Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material.

摘要翻译： 制造单片三维NAND串的方法包括在衬底上形成交替的第一材料层和第二材料层的堆叠，其中每个第二材料层包括在第二硅层的两层之间的第一氧化硅材料层 氧化物材料，不同于第一氧化硅材料，蚀刻堆叠以在堆叠中形成前侧开口，在前侧开口的侧壁上形成记忆膜，并且在前侧开口中形成半导体通道，使得至少 存储膜的一部分位于半导体通道和前侧开口的侧壁之间，其中在相应的两层第二氧化硅之间形成气隙或介电常数低于3.9的材料中的至少一个 材料。

公开(公告)号：WO2016028466A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/043096

申请日：2015-07-31

申请人： SANDISK TECHNOLOGIES INC.

发明人： ZHANG, Yanli ,  MAKALA, Raghuveer S. ,  ALSMEIER, Johann ,  LEE, Yao-Sheng ,  XU, Tiger

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/16 ,  H01L29/495 ,  H01L29/7845 ,  H01L29/7883 ,  H01L29/7926

摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes (3a, b) extending substantially parallel to a major surface of a substrate (100), a memory opening (150) extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film (7, 9, 11), and a dummy opening (160) extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate.

摘要翻译： 单片三维NAND串包括基本上平行于基板（100）的主表面延伸的多个控制栅电极（3a，b），基本上垂直于基板主表面延伸的存储器开口（150） 具有包括记忆膜（7,9,11）的存储器开口材料和基本上垂直于衬底的主表面延伸的虚拟开口（160），并且填充有与存储器开口材料不同的虚拟通道材料。 虚拟通道材料具有比存储器开口材料更高的杨氏模量，以抵消由于基板上的多个控制栅电极施加的压缩和拉伸应力之一而导致的基板翘曲。

公开(公告)号：WO2016025191A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/043072

申请日：2015-07-31

申请人： SANDISK TECHNOLOGIES INC.

发明人： LEE, Yao-Sheng ,  PACHAMUTHU, Jayavel ,  MAKALA, Raghuveer S. ,  MATAMIS, George ,  ALSMEIER, Johann ,  CHIEN, Henry

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.

摘要翻译： 制造单片三维NAND串的方法包括在衬底上形成交替的第一和第二材料层的叠层，蚀刻叠层以形成前侧开口，通过前侧开口部分去除第二材料层以形成正面 凹部，在前侧凹部中形成第一阻挡电介质，在前侧凹部中的第一阻挡电介质的上方形成电荷存储区域，在前侧开口的电荷存储区域上形成隧道电介质层和半导体沟道，蚀刻 堆叠以形成背侧开口，通过背侧开口移除第二材料层，以形成使用第一阻挡电介质作为蚀刻停止件的后侧凹槽，在后侧凹部中形成第二阻挡电介质，并在 在后侧凹槽中的第二阻挡电介质。

公开(公告)号：WO2016003638A1

公开(公告)日：2016-01-07

申请号：PCT/US2015/035961

申请日：2015-06-16

申请人： SANDISK TECHNOLOGIES INC.

发明人： MAKALA, Raghuveer S. ,  LEE, Yao-Sheng ,  KANAKAMEDALA, Senaka Krishna ,  ZHANG, Yanli ,  MATAMIS, George ,  ALSMEIER, Johann

IPC分类号： H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11556 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02186 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/28568 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L29/42324 ,  H01L29/495 ,  H01L29/511 ,  H01L29/518 ,  H01L29/7827

摘要： A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.

摘要翻译： 制造三维NAND串的方法包括在衬底上提供交替的第一材料层和第二材料层的堆叠。 所述方法还包括在所述堆叠中形成前开口，在所述前侧开口中形成隧道电介质，在所述隧道电介质的前侧开口中形成半导体沟道，并在所述堆叠中形成背面开口。 该方法还包括通过后侧开口选择性地去除第二材料层，以在相邻的第一材料层之间形成背侧凹槽，在后侧开口和后侧凹槽中形成金属电荷存储层，并在后侧凹槽中形成离散电荷存储区域 通过从后侧开口去除金属电荷存储层并选择性地使金属电荷存储层在后侧凹部中凹陷来使背面凹陷。

公开(公告)号：WO2015041743A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/047480

申请日：2014-07-21

申请人： SANDISK TECHNOLOGIES, INC.

发明人： PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  MAKALA, Raghuveer S. ,  LEE, Yao-Sheng

IPC分类号： H01L27/115

CPC分类号： H01L21/28282 ,  H01L21/28273 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device, such as a three-dimensional monolithic NAND memory string, includes etching a select gate electrode over a first gate insulating layer over a substrate to form an opening, forming a second gate insulating layer over the sidewalls of the opening, forming a sacrificial spacer layer over the second gate insulating layer on the sidewalls of the opening, and etching the first gate insulating layer over the bottom surface of the opening to expose the substrate, removing the sacrificial spacer layer to expose the second gate insulating layer over the sidewalls of the opening, and forming a protrusion comprising a semiconductor material within the opening and contacting the substrate, wherein the second gate insulating layer is located between the select gate electrode and first and second side surfaces of the protrusion.

摘要翻译： 一种制造诸如三维单片NAND存储器串的半导体器件的方法包括在衬底上的第一栅极绝缘层上蚀刻选择栅电极以形成开口，在第二栅极绝缘层的侧壁上形成第二栅极绝缘层 开口，在开口的侧壁上的第二栅极绝缘层上形成牺牲间隔层，并且在开口的底表面上蚀刻第一栅极绝缘层以暴露衬底，去除牺牲间隔层以暴露第二栅极绝缘 在开口的侧壁上方形成包括半导体材料在内的突起并与衬底接触的突起，其中第二栅极绝缘层位于选择栅电极与突起的第一和第二侧表面之间。

公开(公告)号：WO2014011415A1

公开(公告)日：2014-01-16

申请号：PCT/US2013/048508

申请日：2013-06-28

申请人： SANDISK TECHNOLOGIES, INC.

发明人： MAKALA, Raghuveer S. ,  ALSMEIER, Johann ,  LEE, Yao-Sheng

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/768

CPC分类号： H01L27/11582 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/7682 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/7889 ,  H01L29/7926

摘要： A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric.

摘要翻译： 单片三维NAND串包括垂直半导体通道和不同器件级别的多个控制栅电极。 该串还包括阻挡介电层，电荷存储区和隧道电介质。 第一控制栅电极通过位于第一和第二控制栅电极的主表面之间的气隙与第二控制栅极分离，和/或电荷存储区包括嵌入电荷存储电介质中的硅化物纳米颗粒。

公开(公告)号：WO2015041824A3

公开(公告)日：2015-03-26

申请号：PCT/US2014/053055

申请日：2014-08-28

申请人： SANDISK TECHNOLOGIES, INC.

发明人： PACHAMUTHU, Jayavel ,  ALSMEIER, Johann ,  MAKALA, Raghuveer S. ,  LEE, Yao-Sheng

IPC分类号： H01L27/06 ,  H01L27/10 ,  H01L27/115

摘要： A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a first stack of alternating layers of a first material and a second material different from the first material over a substrate, removing a portion of the first stack to form a first trench, filling the trench with a sacrificial material, forming a second stack of alternating layers of the first material and the second material over the first stack and the sacrificial material, removing a portion of the second stack to the sacrificial material to form a second trench, and removing the sacrificial material to form a continuous trench through the first stack and the second stack.