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    WORD LINE CONNECTION FOR MEMORY DEVICE AND METHOD OF MAKING THEREOF
    2.
    发明申请
    WORD LINE CONNECTION FOR MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开
    用于存储器件的字线连接及其制造方法

    公开(公告)号：WO2016028484A1

    公开(公告)日：2016-02-25

    申请号：PCT/US2015/043544

    申请日：2015-08-04

    申请人： SANDISK 3D LLC

    发明人： TAKAKI, Seje

    IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/115

    CPC分类号： H01L27/2481 ,  H01L21/32139 ,  H01L21/76892 ,  H01L27/0688 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/145 ,  H01L45/149 ,  H01L45/16

    摘要： A three-dimensional monolithic memory device includes at least one device region and a plurality of contact regions each including a stack of an alternating plurality of conductive word line contact layers and insulating layers located over a substrate, where the stacks in the plurality of contact regions are separated from one another by an insulating material, and a bridge connector including a conductive material extending between a first conductive word line contact layer of a first stack in a first contact region and a second conductive word line contact layer of a second stack in a second contact region, where the first word line contact layer extends in a first contact level substantially parallel to a major surface of the substrate and the second word line contact layer extends in a second contact level substantially parallel to the major surface of the substrate that is different than the first level.

    摘要翻译： 三维单块存储器件包括至少一个器件区域和多个接触区域，每个接触区域包括交替的多个导电字线接触层和位于衬底上的绝缘层的叠层，其中多个接触区域中的堆叠 通过绝缘材料彼此分离，并且桥连接器包括在第一接触区域中的第一堆叠体的第一导电字线接触层和第二堆叠体的第二导电字线接触层之间延伸的导电材料 第二接触区，其中第一字线接触层在基本上平行于衬底的主表面的第一接触电平中延伸，并且第二字线接触层在基本上平行于衬底的主表面的第二接触电平中延伸， 不同于第一级。

    VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION
    3.
    发明申请
    VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION 审中-公开
    用于高电压操作的垂直位线TFT解码器

    公开(公告)号：WO2014137652A2

    公开(公告)日：2014-09-12

    申请号：PCT/US2014018125

    申请日：2014-02-25

    申请人： SANDISK 3D LLC

    发明人： RABKIN PETER ,  HIGASHITANI MASAAKI

    IPC分类号： H01L27/24

    CPC分类号： H01L27/1052 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

    摘要： A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.

    摘要翻译： 公开了一种具有垂直取向的薄膜晶体管（TFT）选择装置的3D存储器阵列，其具有通道延伸，否则称为栅极/结偏移。 具有通道扩展的垂直取向的TFT选择装置用作3D存储器阵列中的垂直位线选择装置。 具有通道延伸的垂直TFT选择装置具有高击穿电压和低漏电流。 沟道延伸可以在TFT的顶部结或底部结。 根据存储器元件是否经历正向FORM或反向FORM，底部或顶部结可以具有通道扩展。 这在需要时提供了高压接点。

    PROCESS FOR FORMING RESISTIVE SWITCHING MEMORY CELLS USING NANO-PARTICLES
    4.
    发明申请
    PROCESS FOR FORMING RESISTIVE SWITCHING MEMORY CELLS USING NANO-PARTICLES 审中-公开
    使用纳米颗粒形成电阻切换记忆细胞的方法

    公开(公告)号：WO2014120843A1

    公开(公告)日：2014-08-07

    申请号：PCT/US2014/013696

    申请日：2014-01-29

    申请人： SANDISK 3D LLC

    发明人： KAI, James K. ,  ORIMOTO, Takashi W. ,  PURAYATH, Vinod R. ,  MATAMIS, George

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/16 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/149 ,  H01L45/1608 ,  H01L45/1683

    摘要： A process for forming reversible resistance-switching memory cells having resistance-switching nano-particles (532) which provide a reduced contact area to top (546) and bottom (504) electrodes of the memory cells, thereby limiting a peak current. Recesses are formed in a layered semiconductor material (545) above the bottom electrodes (504), and one or more coatings of nano-particles (532) are applied. The nano-particles (532) self-assemble in the recesses so that they are positioned in a controlled manner. A top electrode material (545) is then deposited. In one approach, the recesses are formed by spaced-apart trenches, and the nano-particles (532) self-assemble along the spaced-apart trenches. In another approach, the recesses for each resistance-switching memory cell are separate from one another, and the resistance-switching memory cells are pillar-shaped. The coatings can be provided in one layer, or in multiple layers which are separated by an insulation layer.

    摘要翻译： 一种用于形成具有电阻切换纳米颗粒（532）的可逆电阻切换存储单元的方法，其提供了对存储单元的顶部（546）和底部（504）电极的接触面积的减小，从而限制了峰值电流。 凹部形成在底部电极（504）上方的层状半导体材料（545）中，并且施加一个或多个纳米颗粒（532）涂层。 纳米颗粒（532）在凹陷中自组装，使得它们以受控的方式定位。 然后沉积顶部电极材料（545）。 在一种方法中，凹槽由间隔开的沟槽形成，并且纳米颗粒（532）沿着间隔开的沟槽自组装。 另一方面，每个电阻切换存储单元的凹槽彼此分开，电阻切换存储单元是柱形的。 涂层可以设置在由绝缘层分隔开的一层或多层中。

    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH LOW CURRENT STRUCTURES AND METHODS THEREOF
    6.
    发明申请
    NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH LOW CURRENT STRUCTURES AND METHODS THEREOF 审中-公开
    具有低电流结构的读/写元件的三维阵列的非易失性存储器及其方法

    公开(公告)号：WO2012082770A1

    公开(公告)日：2012-06-21

    申请号：PCT/US2011/064695

    申请日：2011-12-13

    申请人： SANDISK 3D LLC ,  SAMACHISA, George ,  ALSMEIER, Johann

    发明人： SAMACHISA, George ,  ALSMEIER, Johann

    IPC分类号： G11C13/00

    CPC分类号： H01L27/11551 ,  G11C5/025 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2213/71 ,  H01L21/306 ,  H01L21/76224 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149 ,  H01L45/1616

    摘要： A three-dimensional array read/write (R/W) memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. It is preferable to operate the R/W elements with low current and high resistive states. The resistance of these resistive states depends also on the dimension of the R/W elements and is predetermined by the process technology. A sheet (400) electrode in series with the R/W element (430) and a method of forming it provide another degree of freedom to adjust the resistance of the R/W memory element (430). The thickness of the sheet electrode (400) is adjusted to obtain a reduced cross - sectional contact in the circuit path from the word line (470) to the bit line (440). This allows the R/W memory element (430) to have a much increased resistance and therefore to operate with much reduced currents. The sheet electrode (400) is formed with little increase in cell size.

    摘要翻译： 在位于半导体衬底上方不同距离的多个平面层上形成三维阵列读/写（R / W）存储元件。 优选以低电流和高电阻状态操作R / W元件。 这些电阻状态的电阻也取决于R / W元件的尺寸，并且由工艺技术预先确定。 与R / W元件（430）串联的片（400）电极及其形成方法提供另一自由度来调节R / W存储元件（430）的电阻。 调整片状电极（400）的厚度，以便在从字线（470）到位线（440）的电路中获得减小的横截面接触。 这允许R / W存储器元件（430）具有大大增加的电阻，因此以大大减小的电流工作。 片状电极（400）的形状几乎不增加电池的尺寸。