公开(公告)号：WO2017133672A1

公开(公告)日：2017-08-10

申请号：PCT/CN2017/072848

申请日：2017-02-03

Applicant: THE UNIVERSITY OF HONG KONG

Inventor： WANG, Jian ,  CHEUNG, King Tai ,  FU, Bin ,  YU, Zhizhou

IPC: G06F17/50

CPC classification number: G01R19/2506 ,  B82Y10/00 ,  B82Y35/00 ,  G01R19/0053 ,  G01R19/04 ,  G01R31/31702 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/88 ,  Y10S977/936

Abstract: A fast algorithm is used to study the transient behavior due to the step-like pulse. This algorithm consists of two parts: The algorithm I reduces the computational complexity to T 0 N 3 for large systems as long as T 0 N 3 whenever T 2 beyond which it becomes T log 2 N for even longer time. Hence it is of order O(1) if T 2 . Benchmark calculation has been done on graphene nanoribbons with N=10 4 and T=10 8 . This new algorithm allows many large scale transient problems to be solved, including magnetic tunneling junctions and ferroelectric tunneling junctions that could not be achieved before.

Abstract translation:

快速算法用于研究由阶跃状脉冲引起的瞬态行为。 该算法由两部分组成：只要T N ^{3 算法II采用快速多极技术，并且当T 超过它时变成T log _{3 2 N甚至更长的时间。 因此，如果T ，它的阶数为O（1）。 对N = 10 4和T = 10 8的石墨烯纳米带进行了基准计算。 这种新算法可以解决许多大规模的瞬态问题，包括磁隧道结和铁电隧道结，这些都是以前无法实现的。}}

公开(公告)号：WO2009017882A2

公开(公告)日：2009-02-05

申请号：PCT/US2008/066190

申请日：2008-06-06

Applicant: TAKULAPALLI, Bharath, R. ,  LAWS, Gerard, M. ,  GUST, John, Devens ,  THORNTON, Trevor, J.

Inventor： TAKULAPALLI, Bharath, R. ,  LAWS, Gerard, M. ,  GUST, John, Devens ,  THORNTON, Trevor, J.

CPC classification number: G01N27/4145 ,  Y10S977/762 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/953 ,  Y10S977/957 ,  Y10S977/958

Abstract: A solid-state field-effect transistor sensor for detecting chemical and biological species and for detecting changes in radiation is disclosed. The device includes a porous or structured channel section to improve device sensitivity. The device is operated in a fully depleted mode such that a sensed biological, chemical or radiation change causes an exponential change in channel conductance.

Abstract translation: 公开了一种用于检测化学和生物物质并检测辐射变化的固态场效应晶体管传感器。 该装置包括多孔或结构化的通道部分以提高装置灵敏度。 该装置以完全耗尽模式运行，使得感测到的生物，化学或辐射变化引起通道电导的指数变化。

公开(公告)号：WO2007065159A3

公开(公告)日：2008-06-19

申请号：PCT/US2006061522

申请日：2006-12-01

Applicant: ZETTACORE INC ,  MISRA VEENA ,  CHEN ZHONG ,  SHRIVASTAVA RITU ,  MATHUR GURU

Inventor： MISRA VEENA ,  CHEN ZHONG ,  SHRIVASTAVA RITU ,  MATHUR GURU

IPC: H01L27/108

CPC classification number: H01L51/0591 ,  B82Y10/00 ,  G11C11/005 ,  G11C13/0009 ,  G11C13/0016 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/3431 ,  H01L51/0558 ,  H01L51/0595 ,  Y10S977/809 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/943

Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.

Abstract translation: 根据一些实施例，制品包括基底; 所述底物上的分子层包含通过分子连接基与所述底物偶联的至少一个电荷存储分子; 直接在分子层上的固体阻挡介电层; 以及直接在固体阻挡介电层上的导电层。 在一些实施例中，固体阻挡介电层被配置为当电压施加到导电层时，跨越分子层提供大于固体阻挡介电层上的电压降的电压降。 在一些实施例中，分子层的厚度大于固体阻挡介电层的厚度。 该制品在分子层和导电层之间不含电解质。

公开(公告)号：WO2005122235A3

公开(公告)日：2007-06-21

申请号：PCT/US2005020104

申请日：2005-06-07

Applicant: NANOSYS INC ,  HEALD DAVID L ,  CRUDEN KAREN CHU ,  DUAN XIANGFENG ,  LIU CHAO ,  PARCE J WALLACE

Inventor： HEALD DAVID L ,  CRUDEN KAREN CHU ,  DUAN XIANGFENG ,  LIU CHAO ,  PARCE J WALLACE

IPC: H01L21/31 ,  G03F7/075 ,  G11C13/00 ,  H01L21/28 ,  H01L21/312 ,  H01L21/469 ,  H01L21/82 ,  H01L27/10 ,  H01L29/739

CPC classification number: G03F7/0757 ,  B82Y10/00 ,  B82Y30/00 ,  G11C13/00 ,  H01L21/02137 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/28273 ,  H01L21/3124 ,  Y10S977/755 ,  Y10S977/845 ,  Y10S977/855 ,  Y10S977/936 ,  Y10S977/938

Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of a arrays on coatings comprising nanostructure association groups, pattering using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).

Abstract translation: 提供了形成或构图纳米结构阵列的方法。 所述方法包括在包含纳米结构缔合基团的涂层上形成阵列，使用抗蚀剂图案和/或使用便于阵列形成的装置。 还提供了用于形成纳米结构阵列的相关器件，以及包括纳米结构阵列（例如，存储器件）的器件。

公开(公告)号：WO2006033681A3

公开(公告)日：2006-11-30

申请号：PCT/US2005018536

申请日：2005-05-26

Applicant: NANTERO INC ,  BERTIN CLAUDE L

Inventor： BERTIN CLAUDE L

IPC: H04B1/06 ,  G11C13/02 ,  H01L21/00 ,  H03K19/20 ,  H04B1/16

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  Y10S977/936 ,  Y10S977/938 ,  Y10S977/94

Abstract: Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit(l?) includes a differential input having a first and second input link (25, 25'), and a differential output having a first and second output link (30, 30'). First, second, third and fourth switching elements (15, 20, 35, 40) each have an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The receiver circuit can sense small voltage inputs and convert them to larger voltage swings.

Abstract translation: 使用基于纳米管的开关和逻辑的接收器电路。 优选地，电路是双轨（差分）。 接收器电路（1'）包括具有第一和第二输入链路（25,25'）的差分输入和具有第一和第二输出链路（30,30'）的差分输出。 第一，第二，第三和第四开关元件（15,20,35,40）各自具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的可控地形成和取消的控制结构 所述输入节点和所述输出节点之间的导电通道。 接收器电路可以感测小电压输入并将其转换为较大的电压摆幅。

公开(公告)号：WO2005089165A2

公开(公告)日：2005-09-29

申请号：PCT/US2005007709

申请日：2005-03-09

Applicant: NANOSYS INC ,  DUAN XIANGFENG ,  CHOW CALVIN Y H ,  HEALD DAVID L ,  NIU CHUNMING ,  PARCE J WALLACE ,  STUMBO DAVID P

Inventor： DUAN XIANGFENG ,  CHOW CALVIN Y H ,  HEALD DAVID L ,  NIU CHUNMING ,  PARCE J WALLACE ,  STUMBO DAVID P

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

Abstract translation: 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米元素包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

公开(公告)号：WO2005069372A1

公开(公告)日：2005-07-28

申请号：PCT/US2003/040295

申请日：2003-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FURUKAWA, Toshiharu ,  HAKEY, Mark, C. ,  HOLMES, Steven, J. ,  HORAK, David, V. ,  KOBURGER, Charles, W., III ,  NESBIT, Larry, A.

Inventor： FURUKAWA, Toshiharu ,  HAKEY, Mark, C. ,  HOLMES, Steven, J. ,  HORAK, David, V. ,  KOBURGER, Charles, W., III ,  NESBIT, Larry, A.

IPC: H01L27/108

CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

Abstract translation: 沟槽型存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成在沟槽内衬的开放圆筒结构。 该器件通过在衬底上提供碳纳米管催化剂结构并图案化衬底中的沟槽而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

公开(公告)号：WO01018866A1

公开(公告)日：2001-03-15

申请号：PCT/US2000/024815

申请日：2000-09-08

IPC: B81B3/00 ,  G01N27/414 ,  G01Q70/06 ,  G01Q70/08 ,  H01L21/335 ,  H01L29/06 ,  H01L49/00 ,  H01L27/14

CPC classification number: H01L29/0665 ,  B22F1/0025 ,  B22F1/025 ,  B22F9/02 ,  C30B29/602 ,  G03F1/20 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L49/006 ,  H01L2924/0002 ,  Y10S977/855 ,  Y10S977/874 ,  Y10S977/882 ,  Y10S977/888 ,  Y10S977/936 ,  Y10T428/12479 ,  H01L2924/00

Abstract: The present invention provides a MOSFET device comprising: a substrate (1104) including a plurality of atomic ridges, each of the atomic ridges including a semiconductor layer comprising Si (1106) and a dielectric layer comprising a Si compound (1108); a plurality nanogrooves between the atomic ridges; at least one elongated molecule located in at least one of the nanogrooves (1110); a porous gate layer located on top of the plurality of atomic ridges (1112). The present invention also provides a membrane comprising: a substrate; and a plurality of nanowindows in the substrate and a method for forming nanowindows in a substrate. The present invention also provides a multi-tip array device comprising: a substrate; a multi-tip array of atomic tips on the substrate, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and means for moving the substrate. The present invention also provides an atomic claw comprising: a mounting block; a paddle having a multi-tip array thereon, the multi-tip array having a pitch of 0.94 to 5.4 nm between adjacent tips in at least one direction; and a cantilever connected to the paddle and the mounting block, wherein the cantilever allows the paddle to be moved in at least one arcuate direction.

Abstract translation: 本发明提供了一种MOSFET器件，包括：包括多个原子脊的衬底（1104），每个原子脊包括包含Si（1106）的半导体层和包含Si化合物（1108）的介电层; 在原子脊之间的多个纳米岩; 至少一个细长分子位于纳米罗（1110）中的至少一个中; 位于所述多个原子脊（1112）顶部的多孔栅层。 本发明还提供了一种膜，包括：基材; 以及基板中的多个纳米窗口以及在基板中形成纳米窗口的方法。 本发明还提供一种多头阵列装置，包括：基片; 在所述衬底上的多尖端的原子尖端阵列，所述多尖端阵列在至少一个方向上在相邻尖端之间具有0.94至5.4nm的间距; 以及用于移动衬底的装置。 本发明还提供一种原子爪，包括：安装块; 在其上具有多尖端阵列的桨叶，所述多尖端阵列在至少一个方向上在相邻尖端之间具有0.94至5.4nm的间距; 以及连接到桨叶和安装块的悬臂，其中悬臂允许桨在至少一个弧形方向上移动。

公开(公告)号：WO2012033869A1

公开(公告)日：2012-03-15

申请号：PCT/US2011/050752

申请日：2011-09-08

Applicant: PRESIDENT AND FELLOWS OF HARVARD COLLEGE ,  PARK, Jang-Ung ,  NAM, SungWoo ,  LIEBER, Charles, M.

Inventor： PARK, Jang-Ung ,  NAM, SungWoo ,  LIEBER, Charles, M.

IPC: C01B31/04 ,  H01L21/336 ,  H01L29/786 ,  H01L29/16

CPC classification number: H01L21/02527 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/186 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02664 ,  H01L23/53276 ,  H01L29/1606 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/7781 ,  H01L29/78618 ,  H01L29/78684 ,  H01L2924/0002 ,  Y10S977/734 ,  Y10S977/936 ,  Y10S977/938 ,  H01L2924/00

Abstract: In a method for fabricating a graphene structure, there is formed on a fabrication substrate a pattern of a plurality of distinct graphene catalyst materials. In one graphene synthesis step, different numbers of graphene layers are formed on the catalyst materials in the formed pattern. In a method for fabricating a graphene transistor, on a fabrication substrate at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor channel and at least one graphene catalyst material is provided at a substrate region specified for synthesizing a graphene transistor source, and at a substrate region specified for synthesizing a graphene transistor drain. Then in one graphene synthesis step, at least one layer of graphene is formed at the substrate region for the graphene transistor channel, and at the regions for the transistor source and drain there are formed a plurality of layers of graphene.

Abstract translation: 在制造石墨烯结构的方法中，在制造衬底上形成多个不同的石墨烯催化剂材料的图案。 在一个石墨烯合成步骤中，在所形成的图案中的催化剂材料上形成不同数量的石墨烯层。 在制造石墨烯晶体管的方法中，在制造衬底上，在用于合成石墨烯晶体管沟道的衬底区域处提供至少一个石墨烯催化剂材料，并且至少一个石墨烯催化剂材料设置在用于合成石墨烯的基板区域 晶体管源，以及在合成石墨烯晶体管漏极所规定的衬底区域。 然后在一个石墨烯合成步骤中，在用于石墨烯晶体管沟道的衬底区域上形成至少一层石墨烯，在晶体管源极和漏极的区域形成多层石墨烯。

公开(公告)号：WO2011023520A1

公开(公告)日：2011-03-03

申请号：PCT/EP2010/061404

申请日：2010-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  CHIDAMBARRAO, Dureseti ,  SEKARIC, Lidija

Inventor： CHIDAMBARRAO, Dureseti ,  SEKARIC, Lidija

IPC: H01L29/06 ,  H01L29/786 ,  H01L21/336

CPC classification number: H01L29/0665 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78687 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/825 ,  Y10S977/932 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/938

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract translation: 半导体结构包括n沟道场效应晶体管（NFET）纳米线，所述NFET纳米线包括围绕NFET纳米线的核缠绕的膜，所述膜包覆被配置为在NFET纳米线中提供拉伸应力。 制造半导体结构的方法包括生长围绕半导体结构的n沟道场效应晶体管（NFET）纳米线的芯缠绕的膜，膜缠绕被配置为在NFET纳米线中提供拉伸应力。