公开(公告)号：WO2022124895A2

公开(公告)日：2022-06-16

申请号：PCT/NL2021/050747

申请日：2021-12-08

申请人： STICHTING CHIP INTEGRATION TECHNOLOGY CENTRE

发明人： NAKKA, John Suman

IPC分类号： H01L21/603 ,  H01L21/60 ,  H01L23/488 ,  H01L2224/11312 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14135 ,  H01L2224/16052 ,  H01L2224/16058 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/279 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/29018 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/30131 ,  H01L2224/30132 ,  H01L2224/30135 ,  H01L2224/30136 ,  H01L2224/30177 ,  H01L2224/30505 ,  H01L2224/3201 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32052 ,  H01L2224/32056 ,  H01L2224/32058 ,  H01L2224/32227 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/3312 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81862 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/8384 ,  H01L2224/83862 ,  H01L2224/9212 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3512

摘要： An integrated circuit (IC) (30) is attached to a substrate (10) through an improved die attachment layer (20), whereby an IC-package is formed. The die attachment layer (20) comprises at least one first region (21) comprising a first attachment material and at least one second region (22) comprising a second attachment material different from the first attachment material, wherein the at least one first region (21) is located centrally on the substrate (10), wherein the at least one second region (22) is located eccentrically, such as at a side, at a part of a side, or at a corner, wherein the at least one first region (21) comprises at least one metal (e.g., sintered silver) and the at least one second region (22) comprises a die-attach material selected from heat assisted attach materials, pressure-based attach materials, pressure-less attach materials, thermohardening attach materials, such as epoxy resins, curing attach materials, polymer based attach materials, resin based attach materials, fibres, nanoparticles, and combinations thereof, in particular, wherein the at least one second region (22) comprises particles of dielectric material embedded in a matrix of polymeric material. A thermal expansion coefficient (TCE3) of the at least one first region (21) and a thermal expansion coefficient (TCE4) of the at least one second region (22) may be between a thermal expansion coefficient (TCE1) of the substrate (10) and a thermal expansion coefficient (TCE2) of the die (30). The thermal expansion coefficient (TCE4) of the at least one second region (22) may be between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE1) of the substrate (10) or between the thermal expansion coefficient (TCE3) of the at least one first region (21) and the thermal expansion coefficient (TCE2) of the die (30). The elastic modulus (EM1) of the at least one first region (21) may be higher than the elastic modulus (EM2) of the at least one second region (22), wherein, preferably, the elastic modulus (EM1) of the at least one first region (21) is lower than an elastic modulus of the die (30) and wherein, preferably, the elastic modulus (EM2) of the at least one second region (22) is higher than an elastic modulus of the substrate (10), wherein the elastic moduli are each a Young's modulus, a bulk modulus, viscoelastic modulus, and/or a volumetric modulus. The attachment layer (20) may extend up to a side of the die (30), preferably forming a fillet (27). The attachment layer may comprise a cavity (28) for receiving the die (30), preferably a cavity (28) adapted to outer dimensions of the die (30). The die (30) may be a power IC or, alternatively, the integrated circuit may relate to a photonics application, with an improved heat flow from die (30) to the substrate (10), or may relate to an IC requiring precise temperature control thereof, such as a VCSEL circuit. In the manufacturing method, i.e., method of die bonding, the at least one first region (21) may be provided in the form of at least one central bar-shaped volume, optionally with one or more side branches, preferably towards every substrate corner and optionally at each longitudinal side of the substrate (10). The die (30) may be attached to the substrate (10) by applying pressure, by applying heat, by applying curing, by sintering, by diffusion, or by a combination thereof. After attaching the die (30), the first region (21) is spread out over the central region of the substrate (10), whereas the second regions (22) are slightly increased in surface are size and are positioned at the sides and corners.

公开(公告)号：WO2021199553A1

公开(公告)日：2021-10-07

申请号：PCT/JP2020/049310

申请日：2020-12-28

申请人： MITSUBISHI ELECTRIC CORPORATION ,  MITSUBISHI ELECTRIC R&D CENTRE EUROPE B.V.

发明人： BRANDELERO, Julio ,  VOYER, Nicolas

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/279 ,  H01L2224/29011 ,  H01L2224/29076 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32012 ,  H01L2224/32014 ,  H01L2224/32227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83121 ,  H01L2224/83192 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512

摘要： A power module assembly comprises a power die (5) attached to a substrate (1) through a joint layer (41) comprising solid pads (4, 4') of metal alloy material connecting electrically and thermally said power die (5) to said substrate (1), wherein said solid pads (4, 4') are located within cells (200, 201, 202) of a grid (2, 2') made of an elastic material and having cell walls (20) extending between the surface of the substrate (1) and the surface of the die (5) facing each other. A process for manufacturing the power module assembly comprises: providing an elastic grid (2, 2') having a length and a width corresponding to the length and width of the semiconductor die (5) to attach; placing and attaching said elastic grid (2, 2') on the substrate (1); placing a stencil (3) forming a frame with a shape adapted to a contour of the semiconductor die (5) on the substrate (1) around the grid (2, 2') and applying paste (9) with a screen printing technique in the area defined by the stencil (3); removing the stencil (3); placing the power semiconductor die (5) on top of the paste (9); applying pressure on the die (5) to compress the assembly made of the die (5), the grid (2, 2') and paste (9) and the substrate (1); heating (10) the assembly either to melt the metal particles of the paste (9) or to sinter the particles; and cooling the assembly to provide solid pads (4, 4') embedded in said grid (2, 2'). The grid (2, 2') acts as an elastic barrier, preventing crack propagation within the joint layer (41) while providing little thermal resistance. The grid (2,2 ') may be a honeycomb shaped (2) or square shaped (21) lattice. A grid cell (200, 201, 202) size may be at least ten times bigger than a grid wall (20) width. The width of walls (20) of the grid cells (200,201, 202) may be larger than half of the thickness of the joint layer (41). The grid material may be such that the walls (20) of the grid (2, 2') contract with an increase of temperature, helping applying a high pressure on the paste (9) during the heating process phase and allowing the solid paste (4, 4') to expand in the hot areas without extra constraint during the operation of the power semiconductor die (5), leaving room to the rest of the joint layer (41) to expand under high temperature, relaxing the stress. The grid (2, 2') may be a polyimide grid, in particular, made out of a single- or double-faced adhesive polyimide tape. The grid (21) may comprise peripheral cells (201) of a reduced width with respect to central cells (202) of the grid (21), limiting propagation of cracks so that the cracks cannot grow from the sides or corners more than the width of the reduced width cells (201) while inner cells (202) may be larger to reduce the degradation of the overall thermal resistance. The cells (200, 201,202) of the grid (2, 2') may be shaped through laser cutting. The elastic grid (2, 2') may be formed as a tape with adhesive on both sides and be glued on both the substrate (1) and the die (5). The elastic grid (2, 2') may be placed and attached on the substrate (1) with a screen printing technique using an ink charged with high thermal conductive particles.

公开(公告)号：WO2021141660A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/059326

申请日：2020-11-06

申请人： RAYTHEON COMPANY

发明人： GETTY, Jonathan ,  LOFGREEN, Daniel D. ,  MILLER, Alexandra V.

IPC分类号： H01L23/00 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05655 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/80211 ,  H01L2224/80345 ,  H01L2224/80359 ,  H01L2224/80815 ,  H01L2224/80896 ,  H01L2224/83209 ,  H01L2224/83409 ,  H01L2224/83896 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/30 ,  H01L24/80 ,  H01L2924/14

摘要： A direct bond hybridization (DBH) method is provided. The DBH method includes preparing a first underlying layer, a first contact layer disposed on the first underlying layer and a first contact electrically communicative with the first underlying layer and protruding through the first contact layer, preparing a second underlying layer, a second contact electrically communicative with the second underlying layer and formed of softer material than the first contact and a second contact layer disposed on the second underlying layer and defining an aperture about the second contact and a moat at least partially surrounding the second contact and bonding the first and second contact layers whereby the first contact contacts the second contact such that the second contact deforms and expands into the moat.

公开(公告)号：WO2021259536A2

公开(公告)日：2021-12-30

申请号：PCT/EP2021/061372

申请日：2021-04-30

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： WAGNER, Claus Florian ,  WOITON, Michael

IPC分类号： H01L21/60 ,  H01L23/488 ,  H01L23/485 ,  H01L23/498 ,  H01L23/58 ,  H01L21/4867 ,  H01L2224/0603 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1132 ,  H01L2224/11332 ,  H01L2224/11334 ,  H01L2224/11848 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/13169 ,  H01L2224/1318 ,  H01L2224/13294 ,  H01L2224/13339 ,  H01L2224/141 ,  H01L2224/1412 ,  H01L2224/16227 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/2732 ,  H01L2224/27332 ,  H01L2224/27334 ,  H01L2224/27848 ,  H01L2224/279 ,  H01L2224/27901 ,  H01L2224/27903 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29157 ,  H01L2224/29169 ,  H01L2224/2918 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/3003 ,  H01L2224/30051 ,  H01L2224/301 ,  H01L2224/3012 ,  H01L2224/3016 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/8184 ,  H01L2224/8384 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83

摘要： Um ein verbessertes Schaltverhalten und eine höhere maximale Stromdichte zu erreichen, wird vorgeschlagen, dass in einem Verfahren zur Kontaktierung eines Leistungshalbleiters (2) auf einem Substrat (4) der Leistungshalbleiter (2) auf einer dem Substrat (4) zugewandten Seite (8) mindestens zwei elektrisch voneinander isolierte Kontaktbereiche (10, 12) aufweist, wobei die mindestens zwei elektrisch voneinander isolierten Kontaktbereiche (10, 12) des Leistungshalbleiters (2) mittels einer strukturierten, insbesondere metallischen, Verbindungsschicht (26), welche mindestens zwei Sinterschichten (20, 24, 36) umfasst, mit dem Substrat (4) stoffschlüssig verbunden werden, wobei die mindestens zwei Sinterschichten (20, 24, 36) im Wesentlichen geschlossen sind, d.h., im Gegensatz zum Siebdruck, mit einer Schablone ohne tragendes Sieb aufgetragen werden, sodass keine funktional feststellbaren Hohlräume in der Verbindungsschicht (26) vorhanden sind. Der Leistungshalbleiter (2) kann durch die Verbindungsschicht (26) mindestens 70 um, insbesondere mindestens 200 um, vom Substrat (4) beabstandet kontaktiert werden. Durch einen derartigen Abstand wird erreicht, dass auf dem Leistungshalbleiter (2) auftretende elektromagnetische Felder, welche beispielsweise im Bereich eines Guardrings (2b) auftreten, nicht merklich mit dem Substrat (4) interagieren, sodass das Schaltverhalten des Leistungshalbleiters (2) und eine Isolation im Randbereich durch eine zu große Nähe zum Substrat (4) nicht merklich beeinflusst werden, was zu einer Erhöhung der Lebensdauer führt. Eine erste Sinterschicht (20) kann auf das Substrat (4) aufgetragen und zumindest teilweise getrocknet werden und zumindest eine zweite Sinterschicht (24) kann auf die erste Sinterschicht (20) aufgetragen und zumindest teilweise getrocknet werden, wobei die mindestens zwei elektrisch voneinander isolierten Kontaktbereiche (10, 12) des Leistungshalbleiters (2) auf der zweiten Sinterschicht (24), insbesondere durch Anpressen, kontaktiert und daraufhin durch Sintern der zumindest zwei Sinterschichten (20, 24, 36) stoffschlüssig mit dem Substrat (4) verbunden werden. Dabei kann die erste Sinterschicht (20) mittels einer ersten Schablone (18) und die zweite Sinterschicht (24) mittels einer zweiten Schablone (22) aufgetragen werden, wobei die zweite Schablone (22) dicker als die erste Schablone (18) ist. Alternativ kann eine erste Sinterschicht (20) auf das Substrat (4) aufgetragen und zumindest teilweise getrocknet werden, wobei zumindest eine zweite Sinterschicht (24) auf eine Transfereinheit (38) aufgetragen und zumindest teilweise getrocknet wird, wobei die zumindest teilweise getrocknete zweite Sinterschicht (24) von der Transfereinheit (38) auf die erste Sinterschicht (20) übertragen wird, wobei die mindestens zwei elektrisch voneinander isolierten Kontaktbereiche (10, 12) des Leistungshalbleiters (2) auf der zweiten Sinterschicht (24), insbesondere durch Anpressen, kontaktiert und daraufhin durch Sintern der zumindest zwei Sinterschichten (20, 24) stoffschlüssig mit dem Substrat (4) verbunden werden. Dabei können die erste Sinterschicht (20) mittels einer ersten Schablone (18) auf das Substrat (4) und die zweite Sinterschicht (24) mittels einer zur ersten Schablone (18) spiegelsymmetrischen Schablone (40) auf die Transfereinheit (38) aufgetragen werden. Noch alternativ kann eine erste Sinterschicht (20) auf das Substrat (4) aufgetragen und zumindest teilweise getrocknet werden, wobei zumindest eine zweite Sinterschicht (24) auf einen Metallformkörper (42) aufgetragen und zumindest teilweise getrocknet wird, wobei der Metallformkörper (42) mit einer der zumindest teilweise getrockneten zweiten Sinterschicht (24) abgewandten Seite auf der ersten Sinterschicht (20) platziert wird, wobei die mindestens zwei elektrisch voneinander isolierten Kontaktbereiche (10, 12) des Leistungshalbleiters (2) auf der zweiten Sinterschicht (24), insbesondere durch Anpressen, kontaktiert und daraufhin durch Sintern der zumindest zwei Sinterschichten (20, 24) stoffschlüssig mit dem Substrat (4) verbunden werden. Dabei kann der Metallformkörper (42) zumindest zwei Metallplättchen (42a, 42b) umfassen, wobei die zumindest eine zweite Sinterschicht (24) mittels zumindest einer ersten Schablone (18) auf die zumindest zwei Metallplättchen (42a, 42b) des Metallformkörpers (42) aufgetragen wird. Der Leistungshalbleiter (2) kann auf der dem Substrat (4) abgewandten Seite (16) einen dritten Kontaktbereich (14) aufweisen, welcher stoffschlüssig mit einem, insbesondere mehrlagigen, weiteren Substrat (48) verbunden ist, wobei die zwei elektrisch voneinander isolierten Kontaktbereiche (10, 12) über jeweils mindestens ein Verbindungselement (50, 52), insbesondere stoffschlüssig, mit dem weiteren Substrat (48) verbunden sind. Das Leistungshalbleitermodul (44) kann in einem Stromrichter umfasst sein.

公开(公告)号：WO2022200749A2

公开(公告)日：2022-09-29

申请号：PCT/FR2022/050572

申请日：2022-03-28

申请人： SAFRAN ELECTRONICS & DEFENSE

发明人： RIOU, Jean-Christophe ,  PONS, Corinne ,  JAUSSENT, Alain

IPC分类号： H01L21/60 ,  H01L21/603 ,  H01L21/98 ,  H01L25/065 ,  H01L23/538 ,  H01L21/67 ,  H01L2224/27848 ,  H01L2224/29012 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/32227 ,  H01L2224/75251 ,  H01L2224/753 ,  H01L2224/75315 ,  H01L2224/759 ,  H01L2224/83055 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83208 ,  H01L2224/8384 ,  H01L2224/83907 ,  H01L23/5385 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/50 ,  H01L2924/00015 ,  H01L2924/19105

摘要： Un procédé pour assembler un composant électronique (28) à un substrat (30) comprend les étapes successives suivantes : on dépose un matériau de frittage (26) sur l'un parmi un composant électronique (28) et un substrat (30); on chauffe le matériau de frittage (26) de façon à placer une température du matériau de frittage (26) dans un pic exothermique préalable (8) qui précède un pic exothermique de frittage (10) sans que la température du matériau de frittage (26) atteigne un maximum du pic exothermique préalable (8); on fixe au matériau de frittage (26) l'autre parmi le composant électronique (28) et le substrat (30) de sorte que le matériau de frittage (26) est interposé entre le composant électronique (28) et le substrat (30); et on presse le matériau de frittage (26) à chaud de façon à réaliser un fluage du matériau de frittage (26). Une étape de frittage du matériau de frittage (26) peut ensuite être effectuée. Le pic exothermique préalable (8) est le marqueur de l'activation des paillettes du matériau de frittage (26) pour un fluage ou un frittage ultérieur. L'étape de dépôt peut avoir lieu en disposant le matériau de frittage (26) en boustrophédon. L'étape de dépôt peut avoir lieu en formant avec le matériau de frittage (26) des boudins (32) en contact mutuel. L'étape de dépôt peut avoir lieu en déposant le matériau de frittage (26) sur le substrat (30) de sorte que, à l'issue du procédé, le matériau de frittage (26) dépasse des bords du composant électronique (28). Alternativement, l'étape de dépôt peut avoir lieu en déposant le matériau de frittage (26) sur le composant électronique (28) en retrait de bords du composant électronique (28). Le procédé peut comprendre une étape préliminaire de chauffage d'un échantillon de test du matériau de frittage (26) en l'exposant à une température croissante, dans laquelle, durant le chauffage, on mesure une température du matériau de frittage (26) et on détecte une première valeur de température de chauffage correspondant à un début du pic exothermique préalable (8) qui précède le pic exothermique de frittage (10) et une deuxième valeur de température de chauffage correspondant au maximum du pic exothermique préalable (8). Le substrat (30) peut être un premier substrat, deux composants électroniques (28) de dimensions différentes l'un de l'autre (par exemple, différant par leur hauteur) étant interposés entre le premier substrat (30) et un deuxième substrat (30), des couches de matériau de frittage (26) étant interposées entre chaque composant électronique (28) et le premier et deuxième substrat (30), auquel cas : on dispose les deux couches inférieures de matériau de frittage (26) sur le substrat inférieur (30) puis on effectue l'étape de séchage de ce matériau de frittage (26); ensuite on installe les deux composants électroniques (28) et on applique par-dessus les deux autres couches de matériau de frittage (26); on procède ensuite à une nouvelle étape de séchage; on applique ensuite le substrat supérieur (30), on presse les composants électroniques (28) entre les deux substrats (30) et on effectue ensuite le fluage simultané de toutes les couches de matériau (26); et on procède au frittage du matériau de frittage (26). Durant le pressage, on peut mesurer une pression d'un organe (24) en appui sur le matériau de frittage (26) et déterminer si la pression varie sur une amplitude prédéterminée pendant une durée prédéterminée et/ou on peut mesurer une position de l'organe (24) en appui sur le matériau de frittage (26) et déterminer si la position varie sur une amplitude prédéterminée pendant une durée prédéterminée.

公开(公告)号：WO2022015695A1

公开(公告)日：2022-01-20

申请号：PCT/US2021/041376

申请日：2021-07-13

申请人： FUJIFILM ELECTRONIC MATERIALS U.S.A., INC.

发明人： MALIK, Sanjay ,  DE, Binod B. ,  REINERTH, William A. ,  DIMOV, Ognian ,  DILOCKER, Stephanie

IPC分类号： C08G73/10 ,  C08J3/24 ,  C08K3/36 ,  C08F283/04 ,  G03F7/0035 ,  G03F7/0037 ,  G03F7/0047 ,  G03F7/027 ,  G03F7/037 ,  H01L2224/27436 ,  H01L2224/29147 ,  H01L2224/2969 ,  H01L2224/2979 ,  H01L24/27 ,  H01L24/29 ,  H01L2924/12041

摘要： This disclosure relates to a dielectric film forming composition that includes a plurality of (meth)acrylate containing compounds, at least one fully imidized polyimide polymer, and at least one solvent.

公开(公告)号：WO2022271237A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021671

申请日：2022-03-24

申请人： INTEL CORPORATION

发明人： ELSHERBINI, Adel A. ,  LIFF, Shawna ,  SWAN, Johanna M. ,  SEBOT, Julien

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2224/16225 ,  H01L2224/24147 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/82005 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L2924/37001

摘要： A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.

公开(公告)号：WO2022164317A2

公开(公告)日：2022-08-04

申请号：PCT/NL2022/050040

申请日：2022-01-26

申请人： CHIP INTEGRATION TECHNOLOGY CENTRE

发明人： DORRESTEIN, Sander

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L23/367 ,  H01L23/373 ,  H01L2224/2732 ,  H01L2224/27334 ,  H01L2224/279 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29076 ,  H01L2224/29083 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/32012 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/83385 ,  H01L2224/8384 ,  H01L2224/83862 ,  H01L23/3735 ,  H01L23/564 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/15747 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121

摘要： An integrated circuit comprises: a die (30) having a first elastic modulus (a Young's modulus, a bulk modulus, or a volumetric elasticity) and a first coefficient of thermal expansion, comprising an electronic circuit and generating heat in use; a substrate (10) having a second elastic modulus and a second coefficient of thermal expansion, for dissipating heat from the die (30); an attachment layer (20) arranged between the die (30) and the substrate (10); wherein the attachment layer (20) comprises: an attachment material (22), having a third elastic modulus and a third coefficient of thermal expansion, and a mesh (21) with openings, having a fourth elastic modulus and a fourth coefficient of thermal expansion, wherein the attachment material (22) substantially fills the openings of the mesh (21); wherein the third elastic modulus is lower than the fourth elastic modulus; wherein the attachment layer (20) has a combined fifth coefficient of thermal expansion, which is below the first coefficient of thermal expansion. The combined fifth coefficient of thermal expansion may be between the first coefficient of thermal expansion and the second coefficient of thermal expansion. The attachment layer (20) may have a combined fifth elastic modulus, being lower than the fourth elastic modulus. The combined fifth elastic modulus may be in a range between the third elastic modulus and the fourth elastic modulus, for example, the fifth elastic modulus may depend on the weight and/or the volume of the attachment material (22) relative to the weight and/or the volume of the mesh (21). The mesh (21) may be a wire mesh, such as a net or netting, intertwined structure and/or network structure. The mesh (21) may be partly or fully embedded in the attachment material (22). The mesh (21) may be in physical contact with the substrate (10). The mesh (21) may be an integrated part of the substrate (10), preferably wherein the mesh (21) is formed from protruding parts of the substrate (10) after removing, such as galvanically growing, milling or etching away, parts of the substrate (10). The mesh (21) may extend beyond a die attachment surface facing the attachment. The mesh (21) may be smaller than the die attachment surface, preferably forming a region and/or an island where the combined fifth coefficient of thermal expansion is locally adapted and/or the combined fifth elastic modulus is locally adapted, advantageously allowing the mesh (21) and/or the attachment layer (20) as a whole to be adapted to the expected amount of heat generated at a particular location in the die (30), more specific to a hot spot of the die (30). The mesh (21) may comprise mechanical parts, such as springs and/or hinges, configured for recovering its original shape when released after deformation and/or reinforcements for relieving and/or reducing thermal expansion tension in the attachment layer (20). The mesh (21) may comprise one or more of copper, nickel, tungsten, tungsten copper alloy, CuW, iron, FeNi, molybdenum and polyimide, or an alloy one or more of the previously mentioned materials. The mesh (21) is designed by identifying the hot spot location of a hot spot of the die (30); and adapting the mesh (21) based on the hot spot location. The adapting may comprise: shrinking the opening area of the mesh (21) relative to the area of the mesh (21) when projected from above at the location of the hot spot; and/or enlarging the opening area of the mesh (21) relative to the area of the mesh (21) when projected from above at the location away from the hot spot. The die (30) may have an operational die temperature, wherein the method for manufacturing the integrated circuit may comprise curing the attachment layer (20) after arranging the die (10) on top of the attachment layer (20), wherein the curing is performed at a curing temperature between the operational temperature and room temperature. The attachment layer (20) may be provided on top of the substrate (10). Providing the attachment layer (20) may comprise: applying a first layer of attachment material (22) on the substrate (10), preferably with stencil printing; placing the mesh (21) on top of the first layer, preferably pressing the mesh (21) into the first layer; and applying a second layer of attachment material (22) on the first layer and/or the mesh (21), preferably with stencil printing. Alternatively, the attachment layer (20) may be pre-produced, such as a preform of die attach material. The preform of die attach material may be manufactured by applying a first layer of attachment material (22) on a temporal surface, preferably with stencil printing; placing the mesh (21) with openings on top of the first layer (22), preferably pressing the mesh (21) into the first layer (22); applying a second layer of attachment material (22) on the first layer and/or the mesh (21), preferably with stencil printing; and preferably removing the first layer, the mesh (21), and the second layer from the temporal surface for obtaining the preform.