公开(公告)号：WO2018071116A1

公开(公告)日：2018-04-19

申请号：PCT/US2017/050440

申请日：2017-09-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： PANG, Liang ,  PACHAMUTHU, Jayavel ,  DONG, Yingda

IPC: H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/1157

CPC classification number: H01L27/11519 ,  H01L21/02532 ,  H01L21/0262 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Abstract translation: 这里公开的是具有选择晶体管的3D存储器及其制造方法。 选择晶体管可以具有导电浮置栅极，导电控制栅极，导电浮置栅极和导电控制栅极之间的第一电介质以及主体和导电浮置栅极之间的第二电介质。 在一个方面中，使用在晶体半导体选择晶体管主体附近的凹槽中的横向外延生长，随后通过外延生长形成栅极电介质来形成均匀的栅极电介质。 技术有助于防止或至少降低选择晶体管控制栅极与选择晶体管下方的选择晶体管主体和/或半导体衬底之间的泄漏电流。 因此，选择具有基本均匀的阈值电压，电流和S因子的晶体管。 另外，选择晶体管具有较高的导通电流和陡峭的亚阈值斜率。

公开(公告)号：WO02015277A2

公开(公告)日：2002-02-21

申请号：PCT/US2001/025092

申请日：2001-08-13

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/115 ,  H01L27/14 ,  G11C11/34

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 本发明涉及包括若干设备级别的电荷存储设备的三维单片网络。 通过机械化学抛光使位于两个连续设备层之间的至少一个表面平坦化。

公开(公告)号：WO2009042345A1

公开(公告)日：2009-04-02

申请号：PCT/US2008/074641

申请日：2008-08-28

Applicant: SANDISK CORPORATION ,  LUTZE, Jeffrey, W. ,  LEE, Dana

Inventor： LUTZE, Jeffrey, W. ,  LEE, Dana

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

Abstract: A plurality of non- volatile storage elements on a common active layer are offset from neighbor non- volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements. For example, a NAND string over active area (100) has a charge storage nitride layer (112) that is vertically offset to the charge storage layer (112) of the NAND string over active area (202).

Abstract translation: 公共活动层上的多个非易失性存储元件偏离邻近非易失性存储元件。 非易失性存储元件的这种抵消有助于减少邻近非易失性存储元件的干扰。 还描述了制造偏移非易失性存储元件的制造方法。 例如，有源区（100）上的NAND串具有电荷存储氮化物层（112），其在有源区（202）上垂直偏移到NAND串的电荷存储层（112）。

公开(公告)号：WO0215277A8

公开(公告)日：2002-07-11

申请号：PCT/US0125092

申请日：2001-08-13

Applicant: MATRIX SEMICONDUCTOR INC ,  LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

Inventor： LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/115 ,  G11C11/34 ,  H01L27/14

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了包括多个器件层级的电荷存储器件的单片三维阵列，其中通过化学机械抛光平面化两个连续器件层级之间的至少一个表面。

公开(公告)号：WO2016128859A1

公开(公告)日：2016-08-18

申请号：PCT/IB2016/050533

申请日：2016-02-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： MIYAIRI, Hidekazu

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/0688 ,  H01L27/11273 ,  H01L27/11553 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/41733 ,  H01L29/4236 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor having highly stable electrical characteristics is provided. Furthermore, high performance and high reliability of a semiconductor device including the transistor is achieved. The transistor includes a first electrode, a second electrode, a third electrode, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The transistor includes a first region and a second region surrounded by the first region. In the first region, the first insulating layer, the second electrode, the oxide semiconductor layer, and the second insulating layer are stacked. In the second region, the first electrode, the oxide semiconductor layer, the second insulating layer, and the third electrode are stacked.

Abstract translation: 提供具有高度稳定的电气特性的小型化晶体管。 此外，实现了包括晶体管的半导体器件的高性能和高可靠性。 晶体管包括第一电极，第二电极，第三电极，氧化物半导体层，第一绝缘层和第二绝缘层。 晶体管包括由第一区域包围的第一区域和第二区域。 在第一区域中，堆叠第一绝缘层，第二电极，氧化物半导体层和第二绝缘层。 在第二区域中，堆叠第一电极，氧化物半导体层，第二绝缘层和第三电极。

公开(公告)号：WO2012106439A2

公开(公告)日：2012-08-09

申请号：PCT/US2012023499

申请日：2012-02-01

Applicant: MICRON TECHNOLOGY INC ,  LIU HAITAO ,  LI JIAN ,  MOULI CHANDRA

Inventor： LIU HAITAO ,  LI JIAN ,  MOULI CHANDRA

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7926

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract translation: 示出了包括主体区域和由具有比身体区域更低带隙的半导体形成的连接区域的存储器件。 连接区域配置可以在擦除操作期间提供增加的栅极引起的漏极泄漏。 所显示的配置可以提供用于存储器操作的身体区域的可靠偏置，例如在升压操作期间擦除和容纳身体区域中的电荷。

公开(公告)号：WO0215277A9

公开(公告)日：2002-09-19

申请号：PCT/US0125092

申请日：2001-08-13

Applicant: MATRIX SEMICONDUCTOR INC ,  LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

Inventor： LEE THOMAS H ,  SUBRAMANIAN VIVEK ,  CLEEVES JAMES M ,  WALKER ANDREW J ,  PETTI CHRISTOPHER ,  KOUZNETZOV IGOR G ,  JOHNSON MARK G ,  FARMWALD PAUL M ,  HERNER BRAD

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/115 ,  G11C11/34 ,  H01L27/14

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。