公开(公告)号：EP1569865B1

公开(公告)日：2008-02-13

申请号：EP03782134.5

申请日：2003-12-05

Applicant: X-FAB Semiconductor Foundries GmbH

Inventor： SCHWARZ, Uwe

IPC: B81C1/00 ,  B81C3/00 ,  B81B3/00

CPC classification number: B81C1/00246 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/0728

Abstract: The invention relates to a method for producing a microelectromechanical system (MEMS) which comprises a sensor and CMOS technology-based electronics for processing the sensor signal, both being monolithically integrated in said system. To fulfil the pre-requisites for producing the electronic part (4) of the sensor (5) and the signal processing electronics using CMOS technology, a semiconductor wafer (2) containing a depression is bonded to a wafer with an epitaxial layer by means of said layer (3) using high-temperature fusion bonding, to form a double wafer and material is subsequently removed from one face of the double wafer. The latter is then polished until the epitaxial layer is exposed, thus creating a membrane (3a).

公开(公告)号：EP1857407A2

公开(公告)日：2007-11-21

申请号：EP07075352.0

申请日：2007-05-07

Applicant: Delphi Technologies, Inc.

Inventor： Freeman, John E. ,  Staller, Steven E. ,  Chase, Troy A.

IPC: B81C3/00

CPC classification number: B81C3/002 ,  B81C2201/019

Abstract: A method for fabricating microchip devices is provided. The method includes the steps of providing a first planar substrate (120), locating at least one first alignment feature (128) in the surface (122) of the first planar substrate (120), and bonding a second substrate (140) to the surface (122) of the first planar substrate (120). The method further includes the step of aligning subsequent process operations performed on at least one of the first (120) and second (140) substrates to visible alignment features of the first substrate (120), wherein the visible alignment features are at least one of the first alignment feature (128) and a visible feature that corresponds to the location of the first alignment feature (128).

Abstract translation: 提供了一种用于制造微芯片器件的方法。 该方法包括以下步骤：提供第一平面基板（120），将第一平面基板（120）的表面（122）中的至少一个第一对准特征（128）定位，以及将第二基板（140） 第一平面基板（120）的表面（122）。 该方法还包括将在第一（120）和第二（140）衬底中的至少一个上执行的随后的处理操作与第一衬底（120）的可见对准特征对准的步骤，其中可见对准特征是 第一对准特征（128）和对应于第一对准特征（128）的位置的可见特征。

公开(公告)号：EP1440308A4

公开(公告)日：2007-10-31

申请号：EP02800336

申请日：2002-09-13

Applicant: CORNING INC

Inventor： GUZMAN GUILLAUME ,  THEMONT JEAN-PIERRE

IPC: B01L3/00 ,  B01J19/00 ,  B81B1/00 ,  B81C1/00 ,  B81C99/00 ,  C03B19/02 ,  C03B19/06 ,  C03B23/20 ,  C03B32/00 ,  F15C5/00

CPC classification number: B81C1/00119 ,  B01L3/5027 ,  B33Y70/00 ,  B33Y80/00 ,  B81B2201/058 ,  B81B2203/0353 ,  B81C1/00071 ,  B81C2201/019 ,  B81C2201/036 ,  C03B19/063 ,  C03B23/20 ,  Y10T137/0391 ,  Y10T137/0402 ,  Y10T137/2224 ,  Y10T137/6416

公开(公告)号：EP1631981A2

公开(公告)日：2006-03-08

申请号：EP04750940.1

申请日：2004-05-19

Applicant: Ziptronix, Inc.

Inventor： TONG, Qin-Yi

IPC: H01L21/30 ,  H01L29/04

CPC classification number: B32B7/04 ,  B32B2250/04 ,  B81C1/00357 ,  B81C2201/019 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L21/3105 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/08059 ,  H01L2224/29186 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/81895 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T428/24355 ,  Y10T428/24942 ,  Y10T428/31504 ,  Y10T428/31678 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/05442

Abstract: A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH2 species. This may be accomplished by exposing the bonding layer to an NH4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.

公开(公告)号：EP1392435B1

公开(公告)日：2005-11-30

申请号：EP02741826.8

申请日：2002-06-04

Applicant: Nanostream, Inc.

Inventor： PEZZUTO, Marci ,  DANTSKER, Eugene

IPC: B01L3/00 ,  B01F5/00

CPC classification number: B01F5/0471 ,  B01F5/064 ,  B01F13/0059 ,  B01F15/0205 ,  B01F15/0264 ,  B01L3/502707 ,  B01L3/502738 ,  B01L2300/0864 ,  B01L2300/0874 ,  B01L2300/0887 ,  B01L2400/0406 ,  B01L2400/0487 ,  B01L2400/06 ,  B01L2400/0683 ,  B01L2400/0688 ,  B81B2201/058 ,  B81C1/00119 ,  B81C2201/019 ,  Y10T137/0318 ,  Y10T137/2496 ,  Y10T137/2501 ,  Y10T137/2562 ,  Y10T436/11 ,  Y10T436/117497 ,  Y10T436/118339 ,  Y10T436/2575

Abstract: Microfluidic devices (140, 160, 170, 180, 230, 260, 280, 300, 320, 350, 400, 450) capable of combining discrete fluid volumes generally include channels (144, 147, 161A-D, 162A-D, 176, 177, 188, 189, 249, 250, 269, 270, 296, 297, 319A, 319B, 335, 336, 379A, 386A, 409, 415, 456) for supplying different fluids toward a sample chamber (146, 120, 122, 124, 126, 178, 191, 240, 271, 291, 314, 334, 375, 410, 459) and means for establishing fluid communication between the fluids within the chamber. Discrete fluid plugs are defined from larger fluid volumes before being combined. Certain embodiments utilize actuation chambers (240, 267, 289, 290, 292, 293, 313, 329, 330, 371, 372) or include subchambers (146A, 146B, 120A, 120B, 122A, 122B, 124A, 124B, 126A, 126B, 178A, 178B, 191A, 191B, 410A, 410B) divided by a rupture region (151, 165A, 165B, 179, 190) such as a frangible seal. Further embodiments utilize one or more deformable membranes (171, 185, 242, 268, 283, 323, 355, 420, 451) and/or porous regions (305, 303) to direct fluid flow. Certain devices may be pneumatically or magnetically actuated.

公开(公告)号：EP1572577A1

公开(公告)日：2005-09-14

申请号：EP03796155.4

申请日：2003-12-04

Applicant: Bruel, Michel

Inventor： Bruel, Michel

IPC: B81C1/00

CPC classification number: B81C1/00047 ,  B81C2201/019 ,  C08F210/16 ,  C08F4/65916 ,  C08F210/14 ,  C08F2500/12 ,  C08F2500/04

Abstract: The invention concerns a method for treating a structure, which consists in: providing an initial structure comprising at least one main part (13) and a secondary part (21) which have a contact interface with each other and means constituting at least one zone to be treated capable of varying in thickness substantially perpendicularly to said interface under the effect of a treatment of the material of which it is made; and applying said treatment to said zone of the initial structure to be treated so as to obtain a final structure (12) such that the variation in the thickness of said zone creates the formation of an internal space (25) extending between said parts over at least one zone of said interface and substantially parallel to said interface or within at least one of said parts, spaced apart and substantially parallel to said interface. The invention also concerns the structure (12) with internal space (25) resulting from the displacement of one part relative to another part of said structure.

Abstract translation: 内部结构体的制造技术具有一个处理区，以产生提供的内部空间（25）的最终结构（12）。 空间延伸的界面区的一部分，并在所述界面的距离为平行于所述内表面。

公开(公告)号：EP1350759A3

公开(公告)日：2004-07-28

申请号：EP02021747.7

申请日：2002-09-25

Applicant: Agilent Technologies Inc. (a Delaware Corporation)

Inventor： Roitman, Daniel B. ,  Killeen, Kevin P. ,  Seaward, Karen L. ,  Yin, Hongfeng ,  Robotti, Karla

IPC: B81C1/00 ,  B29C59/02 ,  B29C65/00 ,  C09J179/08

CPC classification number: B29C66/82661 ,  B01L3/502707 ,  B01L3/502715 ,  B01L3/502738 ,  B01L2200/0689 ,  B01L2200/12 ,  B01L2300/123 ,  B01L2400/0622 ,  B01L2400/0644 ,  B29C43/56 ,  B29C59/02 ,  B29C59/14 ,  B29C59/142 ,  B29C65/48 ,  B29C65/4835 ,  B29C65/521 ,  B29C66/001 ,  B29C66/02 ,  B29C66/026 ,  B29C66/1122 ,  B29C66/53461 ,  B29C66/536 ,  B29C66/54 ,  B29C66/71 ,  B29C66/73115 ,  B29C66/73117 ,  B29C66/73771 ,  B29C66/73772 ,  B29C66/73774 ,  B29C66/73775 ,  B29C66/73776 ,  B29C66/73921 ,  B29C66/73941 ,  B29C66/7465 ,  B29C66/91411 ,  B29C66/91445 ,  B29C66/919 ,  B29C66/9192 ,  B29C66/91941 ,  B29C66/91943 ,  B29C2071/022 ,  B29K2071/00 ,  B29K2079/08 ,  B29K2309/08 ,  B29K2995/0039 ,  B29K2995/0041 ,  B29L2031/756 ,  B81B1/00 ,  B81C1/00357 ,  B81C2201/019 ,  G01N27/44791 ,  G01N30/60 ,  G01N30/6052 ,  G01N30/6095 ,  Y10T156/1023 ,  Y10T428/24479

Abstract: A fabrication and adhesion method for a polyaryl-ether-ketone (PAEK) device, such as a microfluidic device (400), is disclosed. At least one glassy uncrystallized PAEK substrate (250) is heated up to near or above the glass transition temperature to allow the substrate (250) to crystallize from the glass state, while embossing the substrate (250) with patterns (325). Bonding the PAEK substrate (250) to another substrate (255) is accomplished using a solvent-resistant adhesive (270), such as a polyimide-based adhesive, in combination with an adhesion enhancement treatment. In certain embodiments, the adhesion enhancement treatment is a plasma treatment or a chemical sulfonation treatment.

Abstract translation: 公开了一种聚芳醚醚酮（PAEK）器件如微流器件（400）的制造和粘附方法。 将至少一个玻璃状未结晶的PAEK基底（250）加热到接近或高于玻璃化转变温度，以允许基底（250）从玻璃状态结晶，同时用图案（325）压印基底（250）。 使用耐溶剂粘合剂（270），例如聚酰亚胺基粘合剂，结合粘合增强处理，将PAEK基底（250）粘合到另一基底（255）上。 在某些实施方案中，粘合增强处理是等离子体处理或化学磺化处理。

公开(公告)号：EP1436237A1

公开(公告)日：2004-07-14

申请号：EP02747799.1

申请日：2002-07-09

Applicant: Imego AB

Inventor： BERGSTEDT, Leif ,  PERSSON, Katrin

IPC: C03C27/00 ,  H05K3/00 ,  H01L21/473

CPC classification number: H01L24/26 ,  B81C1/00357 ,  B81C2201/019 ,  H01L24/83 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01011 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01058 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/28

Abstract: The present invention relates to a method of anodic bonding a first structure (14) to a glass layer (12). The method comprises the steps of arranging a conductive pattern (11) on a substrate, providing the glass layer on said conductive pattern (11), providing said first structure on said glass layer (12), providing an electrode on one side of said first structure, and applying a voltage to said conductive pattern and said electrode to obtain an electrical field across said first structure and said glass layer, between said conductive pattern (11) and said electrode (15) produce an anodic bonding between said first structure and said glass layer.

公开(公告)号：EP0976005B1

公开(公告)日：2004-03-17

申请号：EP98961043.1

申请日：1998-10-26

Applicant: ROBERT BOSCH GMBH

Inventor： FUNK, Karsten ,  FREY, Wilhelm

IPC: G02B26/08

CPC classification number: B81B3/004 ,  B81B2201/0292 ,  B81B2201/042 ,  B81C1/00142 ,  B81C2201/019 ,  G02B26/0841

公开(公告)号：EP1364398A1

公开(公告)日：2003-11-26

申请号：EP02708936.6

申请日：2002-01-02

Applicant: The Charles Stark Draper Laboratory, INC.

Inventor： BORENSTEIN, Jeffrey

IPC: H01L21/46 ,  C23F1/00

CPC classification number: B81C1/00119 ,  B81B2201/0235 ,  B81C1/00357 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/019 ,  B81C2201/0191

Abstract: The invention provides a general fabrication method for producing MicroElectroMechanical Systems (MEMS) and related devices using Silicon-On-Insulator (SOI). One first obtains an SOI wafer that has (i) a handle layer, (ii) a dielectric layer, and (iii) a device layer. A mesa etch has been made on the device layer of the SOI wafer and a structural etch has been made on the dielectric layer of the SOI wafer. One then obtains a substrate (such as glass or silicon), where a pattern has been etched onto the substrate. The SOI wafer and the substrate are bonded together. Then the handle layer of the SOI wafer is removed, followed by the dielectric layer of the SOI wafer.