公开(公告)号：EP3174826A1

公开(公告)日：2017-06-07

申请号：EP15741540.7

申请日：2015-07-23

Applicant: Carl Freudenberg KG ,  EDC Electronic Design Chemnitz GmbH

Inventor： CAESAR, Thomas ,  TAPPER, Renate ,  HEINZ, Steffen ,  NEUBERT, Marco

IPC: B81C1/00 ,  G01L9/00

CPC classification number: B81B7/0061 ,  B81B7/008 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/0023 ,  G01L9/0042 ,  G01L9/0051 ,  G01L9/0073 ,  G01L2009/0069 ,  H01L24/16 ,  H01L24/45 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: The invention relates to a sensor (2, 2', 2") comprising an electronic chip (4, 4', 4") and a sensor chip (5, 5', 5") which are arranged within a functional volume (3) which is at the lost 4 - 5 mm long, a maximum 2 - 3 mm wide and the maximum height is 0.5 - 0.8 mm. The aim of the invention is to provide a compact sensor.

Abstract translation: 本发明涉及一种包括电子芯片（4,4'，4“）和传感器芯片（5,5'，5”）的传感器（2,2'，2“），传感器芯片（5,5'，5”）布置在功能体积（3 ），其最长4-5mm长，最大宽度为2-3mm，最大高度为0.5-0.8mm。本发明的目的是提供一种经济的过滤元件，其包括紧凑的传感器。

公开(公告)号：EP1927575B1

公开(公告)日：2017-01-25

申请号：EP07008443.9

申请日：2007-04-25

Applicant: Hitachi, Ltd.

Inventor： Fujimori, Tsukasa, c/o Hitachi, Ltd. ,  Hanaoka, Yuko, c/o Hitachi, Ltd. ,  Fukuda, Hiroshi, c/o Hitachi, Ltd.

IPC: B81B7/00

CPC classification number: B81B7/0058 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2207/015 ,  B81C2203/0136

公开(公告)号：EP3093880A1

公开(公告)日：2016-11-16

申请号：EP16163058.7

申请日：2016-03-30

Applicant: Honeywell International Inc.

Inventor： BROWN, Gregory C.

IPC: H01L21/762 ,  B81B3/00

CPC classification number: B81B3/0078 ,  B81B3/004 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2207/094 ,  B81C1/00904 ,  B81C2203/037 ,  G01L9/0055 ,  H01L21/76254 ,  H01L21/86

Abstract: A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.

Abstract translation: 本发明提供一种硅 - 蓝宝石上芯片具有最小的热应变的预载荷。 该芯片包括具有第一蓝宝石表面和相对的第二蓝宝石表面的蓝宝石衬底; 和硅层覆盖所述第一蓝宝石表面。 硅树脂层通过以下步骤形成：在几十从硅晶片的第一有机硅表面微米内的平面创建掩埋腔体的多元性; 激光熔接第一硅表面到第一表面的蓝宝石在室温下附着在硅晶片的蓝宝石晶片; 和切割沿平面包括掩埋空腔的多个硅晶片。 甲硅晶片层从第一硅表面和埋入腔的多个平面之间的硅材料形成。 硅晶片层和蓝宝石晶片形成硅 - 蓝宝石晶片。 硅 - 蓝宝石上芯片通过切割硅 - 蓝宝石晶片形成。

公开(公告)号：EP2226620B1

公开(公告)日：2016-11-16

申请号：EP10153783.5

申请日：2010-02-17

Applicant: Omron Corporation

Inventor： Adachi, Yoshitaka ,  Inoue, Katsuyuki

IPC: G01L9/06 ,  B81B3/00 ,  G01L9/00

CPC classification number: G01L9/0042 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  G01L9/0048 ,  G01L9/0054

公开(公告)号：EP2619536B1

公开(公告)日：2016-11-02

申请号：EP11827357.2

申请日：2011-09-20

Applicant: Fairchild Semiconductor Corporation

Inventor： BRYZEK, Janusz

IPC: G01L9/12 ,  G01L7/08 ,  B81B3/00 ,  B81C1/00 ,  G01L19/04 ,  G01L1/14

CPC classification number: B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00015 ,  B81C1/00158 ,  G01L9/0016 ,  G01L9/0042 ,  G01L9/0073 ,  G01L19/04

Abstract: This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion.

公开(公告)号：EP2410767B1

公开(公告)日：2016-08-24

申请号：EP11174608.7

申请日：2011-07-20

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： ROBERT, Philippe ,  WALTHER, Arnaud

IPC: H04R9/08 ,  H04R11/04 ,  H04R19/00 ,  H04R19/04

CPC classification number: H04R19/005 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/051 ,  H04R9/08 ,  H04R11/04 ,  H04R19/04

公开(公告)号：EP2524389B1

公开(公告)日：2016-06-15

申请号：EP11700251.9

申请日：2011-01-10

Applicant: Elmos Semiconductor Aktiengesellschaft

Inventor： TEN HAVE, Arnd

IPC: B81C99/00

CPC classification number: B81C1/00158 ,  B81B3/0018 ,  B81B3/0021 ,  B81B3/007 ,  B81B3/0072 ,  B81B3/0081 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00626 ,  B81C99/0035 ,  B81C2201/019 ,  G01L9/0047 ,  H01L29/4916 ,  H01L29/84

公开(公告)号：EP2727132B1

公开(公告)日：2016-02-03

申请号：EP12805169.5

申请日：2012-06-29

Applicant: InvenSense, Inc.

Inventor： SEEGER, Joseph ,  TCHERTKOV, Igor ,  AKYOL, Hasan ,  YARALIOGLU, Goksen, G. ,  NASIRI, Steven, S. ,  GURIN, Ilya

IPC: H01L21/00 ,  G01F1/20

CPC classification number: B81B7/02 ,  B81B2201/025 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00246 ,  B81C2203/0771 ,  G01L1/144 ,  G01L1/148 ,  G01L5/0028 ,  G01L9/0072 ,  G01L15/00 ,  G01L19/0092 ,  G01L19/0636 ,  G01L19/148 ,  G01L27/007

公开(公告)号：EP2969911A1

公开(公告)日：2016-01-20

申请号：EP14775941.9

申请日：2014-03-12

Applicant: Robert Bosch GmbH

Inventor： FEYH, Ando ,  GRAHAM, Andrew

IPC: B81B3/00 ,  B81B7/00 ,  H04R19/00

CPC classification number: H04R19/04 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/0714 ,  H04R19/005 ,  H04R31/00

Abstract: A microelectromechanical system (MEMS) microphone has a substrate including a backside trench, and a flexible membrane deposited on the substrate extending over the backside trench. The flexible membrane includes a first electrode. A silicon spacer layer is deposited on a perimeter portion of the flexible membrane. The spacer layer defines an acoustic chamber above the membrane and the backside trench. A silicon rich silicon nitride (SiN) backplate layer is deposited on top of the silicon spacer layer extending over the acoustic chamber. The backplate defines a plurality of opening into the acoustic chamber and includes a metallization that serves as a second electrode.

公开(公告)号：EP2619536A4

公开(公告)日：2015-09-23

申请号：EP11827357

申请日：2011-09-20

Applicant: FAIRCHILD SEMICONDUCTOR

Inventor： BRYZEK JANUSZ

IPC: G01L9/12 ,  B81B3/00 ,  B81C1/00 ,  G01L1/14 ,  G01L7/08 ,  G01L19/04

CPC classification number: B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2207/012 ,  B81C1/00015 ,  B81C1/00158 ,  G01L9/0016 ,  G01L9/0042 ,  G01L9/0073 ,  G01L19/04

Abstract: This document discusses, among other things, an apparatus including a silicon die including a vibratory diaphragm, the die having a silicon die top opposite a silicon die bottom, with a top silicon die port extending from the silicon die top through the silicon die to a top of the vibratory diaphragm, and with a bottom silicon die port extending from the silicon die bottom to a bottom of the vibratory diaphragm, wherein the bottom silicon die port has a cross sectional area that is larger than a cross-sectional area of the top silicon die port, a capacitor electrode disposed along a bottom of the silicon die, across the bottom silicon die port, the capacitor electrode including a first signal generation portion that is coextensive with the top silicon die port, and a second signal generation portion surrounding the first portion.