公开(公告)号：EP4402721A1

公开(公告)日：2024-07-24

申请号：EP22870489.6

申请日：2022-08-22

Applicant: INTEL Corporation

Inventor： GANESAN, Sanka ,  LAMBERT, William J. ,  PENMECHA, Bharat Prasad ,  BRUN, Xavier Francois

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5389 ,  H01L23/49816 ,  H01L23/5385 ,  H01L2924/0001420130101 ,  H01L2224/4809120130101 ,  H01L2224/1622520130101 ,  H01L2924/1816120130101 ,  H01L2924/18120130101 ,  H01L24/48 ,  H01L25/105 ,  H01L25/0657 ,  H01L2225/065120130101 ,  H01L25/0652 ,  H01L2225/0657220130101 ,  H01L2225/0651320130101 ,  H01L2225/0651720130101 ,  H01L2225/0652420130101 ,  H01L2225/0654120130101 ,  H01L2225/0654820130101 ,  H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L2221/6835920130101 ,  H01L2221/6834520130101 ,  H01L2221/6837220130101 ,  H01L24/18 ,  H01L2224/1622120130101 ,  H01L2224/1718120130101 ,  H01L24/17

公开(公告)号：EP4439666A2

公开(公告)日：2024-10-02

申请号：EP24165765.9

申请日：2024-03-25

Applicant: MediaTek Inc.

Inventor： KUO, Che-Hung ,  YU, Ta-Jen ,  HUANG, Chi-Hung

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L2225/065120130101 ,  H01L2225/0656220130101 ,  H01L2225/102320130101 ,  H01L2225/104120130101 ,  H01L2225/105820130101 ,  H01L2225/103520130101 ,  H01L23/3128 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/16

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom package (300A) and a top package (400). The top package is mounted on the bottom package. At least one portion (400EP) of the top package protrudes from a sidewall of the bottom package. The semiconductor device further includes a passive device mounted on a protruding region of the portion of the top package.

公开(公告)号：EP3834227B1

公开(公告)日：2024-09-04

申请号：EP18938731.9

申请日：2018-10-30

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/16 ,  H01L23/433 ,  H01L23/544 ,  H01L25/065 ,  H01L21/98 ,  H01L23/488 ,  H01L23/48 ,  H01L23/49 ,  H01L21/60

CPC classification number: H01L2223/5443320130101 ,  H01L23/544 ,  H01L2223/5448620130101 ,  H01L23/3128 ,  H01L23/16 ,  H01L21/56 ,  H01L23/4334 ,  H01L2224/3222520130101 ,  H01L2224/3214520130101 ,  H01L2224/4822720130101 ,  H01L2224/4809120130101 ,  H01L2224/7321520130101 ,  H01L2224/7326520130101 ,  H01L2924/351120130101 ,  H01L2924/1531120130101 ,  H01L2224/3224520130101 ,  H01L2224/9224720130101 ,  H01L2224/9216520130101 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/065120130101 ,  H01L2225/0656220130101 ,  H01L2224/4824720130101 ,  H01L2924/1531220130101 ,  H01L23/562

公开(公告)号：EP3832884B1

公开(公告)日：2024-08-14

申请号：EP20207764.0

申请日：2020-11-16

IPC: H01L23/367 ,  H01L23/482 ,  H01L23/498 ,  H01L23/00 ,  H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H01L23/66 ,  H01L23/495

CPC classification number: H03F1/0288 ,  H03F3/195 ,  H01L23/66 ,  H03F2200/22220130101 ,  H03F2200/38720130101 ,  H03F2200/45120130101 ,  H03F3/245 ,  H01L23/4824 ,  H01L2223/661120130101 ,  H01L2224/4824720130101 ,  H01L2924/1531120130101 ,  H01L2924/1531320130101 ,  H01L2224/4822720130101 ,  H01L2224/1614520130101 ,  H01L2224/3214520130101 ,  H01L2225/0651320130101 ,  H01L2225/065120130101 ,  H01L2225/0656820130101 ,  H01L2223/665520130101 ,  H01L23/3677 ,  H01L23/49861 ,  H01L23/49541 ,  H01L2224/3222720130101 ,  H01L2224/4911220130101 ,  H01L2224/4917320130101 ,  H01L24/48 ,  H01L2224/7326520130101

公开(公告)号：EP4391050A1

公开(公告)日：2024-06-26

申请号：EP23192801.1

申请日：2023-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： KIM, Junhyoung ,  KIM, Jiwon ,  LEE, Minyong ,  KIM, Dohyung ,  SUNG, Sukkang

IPC: H01L25/065 ,  H01L23/485 ,  H10B43/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L24/06 ,  H01L2225/0656220130101 ,  H01L2225/0652720130101 ,  H01L2225/0656520130101 ,  H01L2225/0654120130101 ,  H01L2225/065120130101 ,  H01L24/20 ,  H10B43/00 ,  H01L24/08 ,  H01L24/05

Abstract: The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction. In each chip stack structure, a redistribution layer between pads of the first semiconductor chip and pads of the second semiconductor chip is present.