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    CAPACITIVE PRESSURE SENSOR AND A METHOD OF FABRICATING THE SAME
    23.
    发明公开
    CAPACITIVE PRESSURE SENSOR AND A METHOD OF FABRICATING THE SAME 审中-公开
    KAPAZITIVER DRUCKSENSOR UND VERFAHREN ZUR HERSTELLUNG DAVON

    公开(公告)号：EP2810036A1

    公开(公告)日：2014-12-10

    申请号：EP12868189.7

    申请日：2012-12-17

    Applicant: Naegele-Preissmann, Dieter ,  Sreedhar, J.V.

    Inventor： Naegele-Preissmann, Dieter ,  Sreedhar, J.V.

    IPC: G01L7/00 ,  H01L21/00

    CPC classification number: G01L1/148 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00182 ,  B81C1/00626 ,  G01L9/0048 ,  G01L9/0073 ,  G01L19/0618 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006

    Abstract: The invention discloses a capacitive pressure sensor and a method of fabricating the same. The capacitive pressure sensor includes a fixed plate configured as a back plate, a movable plate configured as diaphragm for sensing pressure, wherein a cavity is formed between the fixed plate and the movable plate, an isolation layer between the fixed plate and the movable plate and electrical contacts thereof for minimizing the leakage current, plurality of damping holes for configuring the contour of the fixed plate as the deflected diaphragm when pressure is exerted, a vent hole extending to the cavity having resistive air path for providing equilibrium to the diaphragm and an extended back chamber for increasing the sensitivity of the capacitive pressure sensor. The capacitive pressure sensor is also configured for minimizing parasitic capacitance.

    Abstract translation: 本发明公开了一种电容式压力传感器及其制造方法。 电容式压力传感器包括构造为背板的固定板，被构造为用于感测压力的隔膜的可动板，其中在固定板和可动板之间形成空腔，在固定板和可动板之间形成隔离层，以及 用于使泄漏电流最小化的电触头，用于在施加压力时将作为偏转隔膜的固定板的轮廓构成的多个阻尼孔，延伸到具有用于向隔膜提供平衡的阻力空气路径的空腔的通气孔， 后室，用于增加电容式压力传感器的灵敏度。 电容式压力传感器也被配置为最小化寄生电容。

    Semiconductor device with capacitive sensor and integrated circuit
    25.
    发明公开
    Semiconductor device with capacitive sensor and integrated circuit 审中-公开
    Halbleitervorrichtung mitKapazitätssensor和integrierte Schaltung

    公开(公告)号：EP2774891A1

    公开(公告)日：2014-09-10

    申请号：EP13157834.6

    申请日：2013-03-05

    Applicant: AMS AG

    Inventor： Forsyth, Richard

    IPC: B81C1/00

    CPC classification number: B81C1/00246 ,  B81B2201/0214 ,  B81B2201/0264 ,  B81B2203/0109 ,  B81B2203/04 ,  B81B2207/015 ,  B81B2207/096 ,  B81C2203/0714 ,  G01L9/0072 ,  H01L23/481

    Abstract: The semiconductor device comprises a substrate (1) of semiconductor material, at least one integrated component (2) in the substrate at or near a main surface (1'), a plurality of electric conductors (3) at or above the main surface, the integrated component being electrically connected with the electric conductors, a capacitor electrode (11) and at least one further capacitor electrode (12) arranged at or above the opposite back surface (1'') of the substrate, and through-substrate vias (8) with metallizations (9). Each of the metallizations (9) connects one of the electric conductors (3) with either the capacitor electrode (11) or the further capacitor electrode (12). At least one coupling electrode (15) is arranged in the vicinity of the capacitor electrode (11) and the further capacitor electrode (12).

    Abstract translation: 半导体器件包括半导体材料的衬底（1），在主表面（1'）处或附近的衬底中的至少一个集成部件（2），在主表面上或上方的多个电导体（3） 所述集成部件与所述导电体电连接，电容器电极（11）和布置在所述基板的相对背面（1“）上方或上方的至少一个另外的电容器电极（12）以及贯穿基板通孔 8）与金属化（9）。 每个金属化层（9）将电导体（3）中的一个与电容器电极（11）或另外的电容器电极（12）连接。 至少一个耦合电极（15）布置在电容器电极（11）和另外的电容器电极（12）附近。

    VERFAHREN ZUR HERSTELLUNG EINES MOS-TRANSISTORS
    28.
    发明公开
    VERFAHREN ZUR HERSTELLUNG EINES MOS-TRANSISTORS 有权
    用于生产MOS晶体管

    公开(公告)号：EP2714582A1

    公开(公告)日：2014-04-09

    申请号：EP12723196.7

    申请日：2012-05-24

    Applicant: ELMOS Semiconductor AG

    Inventor： KLEINSCHMIDT, Frank ,  TEN HAVE, Arnd

    IPC: B81C1/00 ,  G01L9/00 ,  H01L21/764

    CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81C1/00246 ,  B81C2201/0192 ,  G01L9/0045

    Abstract: The invention relates to a method for producing a semiconductor structure comprising a buried cavity (64), wherein a first semiconductor substrate (10) having an upper face (22) is provided and a depression is formed in the upper face (22) of the first semiconductor substrate (10). In addition, a second semiconductor substrate (26) having crystal lattice planes and an upper face (28) is provided, said upper face extending substantially parallel to the crystal lattice planes, and one of the crystal lattice planes, which is located at a desired distance from the upper face (28) of the second semiconductor substrate (26), is weakened by means of ion implantation such as to generate a predetermined breaking plane. The upper face (28) of the second semiconductor substrate (26) is bonded to the upper face (22) of the first semiconductor substrate (10) under vacuum conditions, wherein the second semiconductor substrate (26) covers the depression (20) in the upper face (22) of the first semiconductor substrate (10) in order to form a buried cavity (60). The second semiconductor substrate (26) is split along the predetermined breaking plane, which leaves a membrane layer (34) of the upper face (22) of the first semiconductor substrate (10).

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