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    ENVELOPE FOLLOWER END POINT DETECTION IN TIME DIVISION MULTIPLEXED PROCESSES
    21.
    发明公开
    ENVELOPE FOLLOWER END POINT DETECTION IN TIME DIVISION MULTIPLEXED PROCESSES 有权
    终点检测在时分方法使用Hüllkurvenalgorithmus

    公开(公告)号：EP1623457A2

    公开(公告)日：2006-02-08

    申请号：EP04751610.9

    申请日：2004-05-06

    Applicant: Unaxis USA Inc.

    Inventor： WESTERMAN, Russell ,  JOHNSON, David

    IPC: H01L21/66

    CPC classification number: H01J37/32935 ,  B81C1/00587 ,  B81C2201/0132 ,  H01J37/32963 ,  H01L21/30655

    Abstract: The present invention provides a method for establishing endpoint during an alternating cyclical etch process or time division multiplexed process. A substrate is placed within a plasma chamber and subjected to an alternating cyclical process having an etching step and a deposition step. A variation in plasma emission intensity is monitored using known optical emission spectrometry techniques. An amplitude information is extracted from a complex waveform of the plasma emission intensity using an envelope follower algorithm. The alternating cyclical process is discontinued when endpoint is reached at a time that is based on the monitoring step.

    CONDUCTIVE ETCH STOP FOR ETCHING A SACRIFICIAL LAYER
    22.
    发明公开
    CONDUCTIVE ETCH STOP FOR ETCHING A SACRIFICIAL LAYER 审中-公开
    CONDUCTING蚀刻掩模用于蚀刻的受害者LAYER

    公开(公告)号：EP1532658A1

    公开(公告)日：2005-05-25

    申请号：EP03734278.9

    申请日：2003-05-30

    Applicant: Silicon Light Machines Corporation

    Inventor： HUNTER, James, A.

    IPC: H01L21/00 ,  H01L27/14 ,  H01L29/82 ,  H01L29/84

    CPC classification number: G02B26/0833 ,  B81B2201/045 ,  B81C1/00531 ,  B81C2201/0132 ,  G02B26/0841

    Abstract: In one embodiment, a micro device is formed by depositing a sacrificial layer over a metallic electrode (step 304), forming a moveable structure over the sacrificial layer (step 306), and then etching the sacrificial layer with a noble gas fluoride (step 308). Because the metallic electrode is comprised of a metallic material that also serves as an etch stop in the sacrificial layer etch, charge does not appreciably build up in the metallic electrode. This helps stabilize the driving characteristic of the moveable structure. In one embodiment, the moveable structure is a ribbon in a light modulator.

    VERFAHREN ZUM ANISOTROPEN PLASMAÄTZEN VON HALBLEITERN
    23.
    发明公开
    VERFAHREN ZUM ANISOTROPEN PLASMAÄTZEN VON HALBLEITERN 有权
    方法用于半导体的各向异性等离子体蚀刻

    公开(公告)号：EP1095401A1

    公开(公告)日：2001-05-02

    申请号：EP00931030.1

    申请日：2000-04-26

    Applicant: ROBERT BOSCH GMBH

    Inventor： LAERMER, Franz ,  SCHILP, Andrea

    IPC: H01L21/3065 ,  H01L21/66

    CPC classification number: B81C1/00626 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0142 ,  H01L21/3065 ,  H01L21/30655

    Abstract: The invention relates to a method for the anisotropic etching of structures on a semiconductor body, in particular for etching recesses in a silicon body (18) which are defined laterally in a precise manner by an etching mask, using a plasma (28). An ion-accelerator voltage is applied to the semiconductor, at least during an etching step which continues for a predetermined period. Said ion-accelerator voltage is induced, in particular, by a high-frequency alternating current. The duration of the etching step is subdivided further into at least two etching periods, between which the applied ion-accelerator voltage is modified. A preferred embodiment contains two etching periods, whereby a higher accelerator voltage is used during the first etching period than during the second etching period. The duration of the first etching period can also be determined dynamically or statically during the etching steps using a device for detecting a polymer breakthrough. In addition, high frequency pulses or pulse packets with an adjustable pulse-pause ratio are preferably used to generate and adjust the level of the accelerator voltage.

    SILICON MEMS MICROPHONE AND MANUFACTURING METHOD THEREFOR
    26.
    发明授权
    SILICON MEMS MICROPHONE AND MANUFACTURING METHOD THEREFOR 有权

    公开(公告)号：EP3094112B1

    公开(公告)日：2019-04-10

    申请号：EP15738235.9

    申请日：2015-04-23

    Applicant: Microlink Senstech Shanghai Ltd.

    Inventor： MIAO, Jianmin

    IPC: H04R31/00 ,  H04R19/04 ,  H04R19/00

    CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81C2201/0132 ,  B81C2203/038 ,  H04R19/005 ,  H04R19/04 ,  H04R31/003 ,  H04R2201/003

    Abstract: This invention relates to the field of silicon microphone technology, more specifically, to a method for fabricating a MEMS microphone using multi-cavity SOI wafer by Si-Si fusion bonding technology, which comprises a multi-cavity silicon backplate (1) and a monocrystalline silicon diaphragm (2), both are separated with a layer of silicon dioxide (9) to form the capacitor of the MEMS microphone. The monocrystalline silicon diaphragm (2) has advantages such as low residual stress and good uniformity, which increase the yield and sensitivity of MEMS silicon microphone; the diaphragm comprises tiny release-assistant holes, spring structures with anchors and bumps, which can quickly release the residual stress and reduce the probability of stiction between the backplate (1) and the silicon diaphragm (2). This structure will further improve yield and reliability of MEMS microphone. Therefore, this invention provides simple and reliable process for fabricating MEMS microphones with high sensitivity, good uniformity, excellent reliability and high yield.

    CMOS AND PRESSURE SENSOR INTEGRATED ON A CHIP AND FABRICATION METHOD
    28.
    发明公开
    CMOS AND PRESSURE SENSOR INTEGRATED ON A CHIP AND FABRICATION METHOD 审中-公开
    集成在芯片上的CMOS和压力传感器及其制造方法

    公开(公告)号：EP3299787A1

    公开(公告)日：2018-03-28

    申请号：EP17181988.1

    申请日：2017-07-18

    Applicant: NXP USA, Inc.

    Inventor： LIU, Lianjun ,  BOSE, Amitava

    IPC: G01L9/00 ,  B81C1/00

    CPC classification number: B81B3/0027 ,  B81B2201/0264 ,  B81B2207/015 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/0132 ,  B81C2201/053 ,  B81C2203/0714 ,  B81C2203/075 ,  G01L9/0042 ,  G01L9/0045 ,  G01L9/0052 ,  G01L9/0054

    Abstract: A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

    Abstract translation: 一种器件包括具有第一和第二硅层的绝缘体上硅（SOI）衬底，绝缘体层插入它们之间。 具有第一导电类型的结构层形成在第一硅层上。 具有与第一导电类型相反的第二导电类型的阱区域形成在结构层中，并且电阻器在阱区域中扩散。 在阱区和电阻器上形成金属化结构。 第一腔体延伸穿过覆盖阱区域的金属化结构，并且第二腔体延伸穿过第二硅层，第二腔体在第一硅层和绝缘体层中的一个处停止。 介于第一腔和第二腔之间的井区域限定压力传感器的隔膜。 可以使用CMOS制造工艺在SOI衬底上同时制造集成电路和压力传感器。

    MEMS-SENSOR, INSB. DRUCKSENSOR
    29.
    发明公开
    MEMS-SENSOR, INSB. DRUCKSENSOR 审中-公开
    MEMS传感器，INS。 压力传感器

    公开(公告)号：EP3268304A1

    公开(公告)日：2018-01-17

    申请号：EP16710114.6

    申请日：2016-03-04

    Applicant: Endress+Hauser GmbH+Co. KG

    Inventor： TEIPEN, Rafael ,  LEMKE, Benjamin

    IPC: B81B3/00 ,  G01L9/00

    CPC classification number: B81B3/0072 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C1/00531 ,  B81C2201/0132 ,  G01L9/0048 ,  G01L9/0073 ,  G01L13/025 ,  G01L19/0618

    Abstract: The invention relates to a MEMS sensor for metrologically sensing a measurement variable having improved resistance to overloading, which MEMS sensor comprises a plurality of layers (1, 3, 5), in particular silicon layers, arranged one on the other, the layers (1, 3, 5) of which MEMS sensor comprise at least one inner layer (5), which is arranged between a first layer (1) and a second layer (3), and in the inner layer (5) of which MEMS sensor at least one cut-out (7) extending through the inner layer (5) perpendicularly to the plane of the inner layer (5) is provided, which cut-out is adjoined on the outside at least in some segments by a region of the inner layer (5) forming a connecting element (9), which region is connected to the first layer (1) and the second layer (3), the MEMS sensor being distinguished in that a lateral surface (11) of the connecting element (9) bounding the cut-out (7) on the outside at least in some segments has, in an end region facing the first layer (1), a rounded shape that reduces the cross-sectional area of the cut-out (7) in the direction of the first layer (1) and, in an end region facing the second layer (3), a rounded shape that reduces the cross-sectional area of the cut-out (7) in the direction of the second layer (3).

    A METHOD OF MANUFACTURE OF MICRO COMPONENTS, AND COMPONENTS FORMED BY SUCH A PROCESS
    30.
    发明公开
    A METHOD OF MANUFACTURE OF MICRO COMPONENTS, AND COMPONENTS FORMED BY SUCH A PROCESS 审中-公开

    公开(公告)号：EP3134916A4

    公开(公告)日：2017-12-13

    申请号：EP15782575

    申请日：2015-04-22

    Applicant: MASTER DYNAMIC LTD

    Inventor： WANG YINGNAN ,  HUANG JIANXING

    IPC: H01L21/308 ,  B81C1/00

    CPC classification number: B28D5/04 ,  B81C1/00626 ,  B81C2201/0132 ,  C09K13/08 ,  G03F7/405

    Abstract: A method of forming a multi-level component includes the step of forming at least one arrangement of micro trenches in a predetermined arrangement in a mask material by a lithography process. Another step involves applying one or more etching processes to a surface of a component upon which the mask is applied. The micro trenches have either first or second different aspect ratios. In the applying step, the component is etched by an aspect ratio dependent etch (ARDE) process so as to form an arrangement of micro trenches and micro pillars between adjacent micro trenches. Another step involves removing the arrangement of micro pillars from the component by a removal process. There is also a multi-level component made according to the above method with a first portion at a first level and a further portion of a further level different from the first level.

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