公开(公告)号：EP3182462A4

公开(公告)日：2018-04-25

申请号：EP15831774

申请日：2015-08-12

申请人： BEIJING INST NANOENERGY & NANOSYSTEMS

发明人： ZHANG CHI ,  TANG WEI ,  ZHANG LIMIN ,  WANG ZHONGLIN

IPC分类号： H01L29/84 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L41/0805 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/423 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/84 ,  H01L41/083 ,  H01L41/113

摘要： The present invention provides a contact electrification effect-based back gate field-effect transistor. The back gate field-effect transistor includes: a conductive substrate; an insulating layer formed on a front face of the conductive substrate; a field-effect transistor assembly including: a channel layer, a drain and a source, and a gate; and a triboelectric nanogenerator assembly including: a static friction layer formed at a lower surface of the gate, a movable friction layer disposed opposite to the static friction layer and separated by a preset distance, and a second electro-conductive layer formed at an outside of the movable friction layer and being electrically connected to the source; wherein, the static friction layer and the movable friction layer are made of materials in different ratings in triboelectric series, and the static friction layer and the movable friction layer are switchable between a separated state and a contact state under the action of an external force. The present invention achieves regulation and control of carrier transport properties in semiconductors by using an electrostatic potential generated in a triboelectric nanogenerator as a gate signal of the back gate field-effect transistor.

公开(公告)号：EP3188249A4

公开(公告)日：2018-04-18

申请号：EP14882775

申请日：2014-12-29

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： WANG ZUQIANG ,  LIU CHIEN HUNG

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49

CPC分类号： H01L27/124 ,  H01L27/12 ,  H01L27/1244 ,  H01L27/1248 ,  H01L29/06 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/786

摘要： A thin-film transistor (TFT), a manufacturing method thereof, a display substrate and a display device are disclosed. The TFT includes: an active layer (20), a gate insulating layer (30), a gate electrode (40), an interlayer dielectric layer (50), a source electrode (61) and a drain electrode (62) disposed on a base substrate (10) in sequence. The source electrode (61) and the drain electrode (62) are respectively connected with the active layer (20) via a through hole (53) exposing the active layer (20); the gate insulating layer (30) at least includes a silicon oxide layer (301) and a silicon nitride layer (302) in a two-layer structure; the interlayer dielectric layer (50) at least includes silicon oxide layers (501) and silicon nitride layers (502) in a four-layer structure; the silicon oxide layers (301, 501) and the silicon nitride layers (302, 502) of the gate insulating layer (30) and the interlayer dielectric layer (50) are alternately arranged; and the dimension of one side of the through hole (53) away from the base substrate (10) is greater than that of one side close to the base substrate (10). The TFT can resolve the problem of wire breakage defect of subsequently formed electrodes in through holes.

公开(公告)号：EP3183752A4

公开(公告)日：2018-03-21

申请号：EP14900215

申请日：2014-08-19

申请人： INTEL CORP

发明人： JAN CHIA HONG ,  HAFEZ WALID ,  CHANG HSU YU ,  OLAC VAW ROMAN ,  CHANG TING ,  RAMASWAMY RAHUL ,  LIU PEI CHI ,  DIAS NEVILLE

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49

CPC分类号： H01L29/42376 ,  H01L21/28088 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/66 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

摘要： Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：EP3258497A1

公开(公告)日：2017-12-20

申请号：EP17170572.6

申请日：2017-05-11

申请人： Samsung Display Co., Ltd.

发明人： LEE, Dong Hee ,  CHA, Gwang Min ,  LEE, Dong Min

IPC分类号： H01L29/49 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/78633 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/4908 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869

摘要： A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate.

摘要翻译： 晶体管位于衬底上。 晶体管包括半导体层。 缓冲层位于晶体管的衬底和半导体层之间，包括绝缘材料。 底层位于衬底和缓冲层之间。 底层和半导体层相互重叠。 底层包括在远离基板的方向上彼此堆叠的第一层，第二层和第三层。

公开(公告)号：EP3203524A1

公开(公告)日：2017-08-09

申请号：EP17153213.8

申请日：2017-01-26

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： YANG, Xiaolei ,  LI, Yong ,  JU, Jianhua

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L27/11 ,  H01L29/10

CPC分类号： H01L27/1104 ,  H01L29/1029 ,  H01L29/4966 ,  H01L29/785

摘要： An SRAM includes a substrate containing a plurality of first substrate regions and a plurality of second substrate regions, a plurality of pull-down transistors formed in the first substrate regions with each pull-down transistor including a first gate structure, and a plurality of pass-gate transistors formed in the second substrate regions with each pass-gate transistor including a second gate structure. A portion of the first substrate region under each first gate structure is doped with first doping ions and a portion of the second substrate region under each second gate structure is doped with second doping ions. Moreover, the concentration of the first doping ions is less than the concentration of the second doping ions, and the work function of the first work function layer in the first gate structures is greater than the work function of the second work function layer in the second gate structures.

摘要翻译： 一种静态随机存取存储器，其包括：包含多个第一基板区域与多个第二基板区域的基板;多个下拉晶体管，形成于第一基板区域中，每一下拉晶体管包括第一栅极结构;以及多个通过 其中每个传输门晶体管包括第二栅极结构，所述栅极晶体管形成在所述第二基板区域中。 每个第一栅极结构下方的第一衬底区域的一部分掺杂有第一掺杂离子，并且每个第二栅极结构下方的第二衬底区域的一部分掺杂有第二掺杂离子。 此外，第一掺杂离子的浓度小于第二掺杂离子的浓度，并且第一栅极结构中的第一功函数层的功函数大于第二功函数层的第二功函数层的功函数 门结构。

公开(公告)号：EP3185301A1

公开(公告)日：2017-06-28

申请号：EP15201916.2

申请日：2015-12-22

申请人： IMEC VZW

发明人： Pourghaderi, Mohammad Ali ,  Alian, AliReza

IPC分类号： H01L29/739 ,  H01L29/49

CPC分类号： H01L29/7831 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/512 ,  H01L29/7391

摘要： A Tunnel Field-Effect Transistor (TFET) is disclosed comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and a intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

摘要翻译： 公开了包括半导体材料的源 - 沟道 - 漏极结构的隧道场效应晶体管（TFET）。 源极 - 沟道 - 漏极结构包括n型或p型掺杂的源极区域，与源极区域相反掺杂的漏极区域以及位于源极区域和漏极区域之间的本征或低掺杂沟道区域。 所述TFET进一步包括参考栅极结构，所述参考栅极结构覆盖所述沟道区域和所述参考栅极结构旁边的源极侧栅极结构，其中所述源极侧栅极结构和所述参考功函数和/或静电的功函数和/或静电势 选择参考栅极结构的电势以允许操作中的TFET器件的隧穿机制发生在沟道区中的源极侧栅极结构与参考栅极结构之间的界面或界面区域处。

公开(公告)号：EP2645419A3

公开(公告)日：2017-03-29

申请号：EP12006387.0

申请日：2012-09-11

申请人： Broadcom Corporation

发明人： Xia, Wei

IPC分类号： H01L27/112 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L27/11233 ,  H01L21/28079 ,  H01L21/28088 ,  H01L27/11293 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

摘要： An integrated circuit (IC) includes a first memory cell transistor (234a) of a read only memory (ROM) array, the first memory cell transistor including a first metal gate (224a, 228a) of a first work function and having a first threshold voltage. The IC also includes a second memory cell transistor (234b) of the ROM array, the second memory cell transistor including a second metal gate (228b) of a second work function and having a second threshold voltage. The first memory cell transistor and the second memory cell transistor can be of a first conductivity type. Furthermore, the first memory cell transistor can include a first high-k gate dielectric and the second memory cell transistor can include a second high-k gate dielectric. Logic transistors (234c, 234d) can be provided and have metal gates (224b, 228c; 228d) and respective threshold voltages.

摘要翻译： 集成电路（IC）包括只读存储器（ROM）阵列的第一存储单元晶体管（234a），第一存储单元晶体管包括第一功函数的第一金属栅极（224a，228a）并具有第一阈值 电压。 IC还包括ROM阵列的第二存储单元晶体管（234b），第二存储单元晶体管包括第二功函数的第二金属栅极（228b）并具有第二阈值电压。 第一存储单元晶体管和第二存储单元晶体管可以是第一导电类型。 此外，第一存储单元晶体管可以包括第一高k栅极电介质，并且第二存储单元晶体管可以包括第二高k栅极电介质。 可以提供逻辑晶体管（234c，234d）并具有金属栅极（224b，228c; 228d）和相应的阈值电压。

公开(公告)号：EP3010043A4

公开(公告)日：2017-03-08

申请号：EP14807330

申请日：2014-01-06

申请人： ENKRIS SEMICONDUCTOR INC

发明人： CHENG KAI

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L29/402 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32139 ,  H01L21/76804 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/42352 ,  H01L29/42356 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66462 ,  H01L29/66681 ,  H01L29/7787 ,  H01L29/7823 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device and a manufacturing method therefor are disclosed. The semiconductor device comprises: a semiconductor device active region (1); an electrode shape controlling layer (2) disposed on the semiconductor device active region (1), the electrode shape controlling layer (2) containing aluminum, the content of aluminum being reduced in a direction from bottom to up from the semiconductor device active region (1), an electrode region being disposed on the electrode shape controlling layer (2), a groove extended toward the semiconductor device active region (1) and penetrating through the electrode shape controlling layer (2) longitudinally being disposed in the electrode region, all or part of a side surface of the groove having a shape of one of a straight slope, a concave slope protruded away from a central line of the groove and a convex slope protruded toward the central line of the groove; and an electrode (5) disposed in the groove in the electrode region entirely or partially, the electrode (5) having a shape matching with the shape of the groove, a bottom portion of the electrode (5) being contacted with the semiconductor device active region (1). By controlling the shape of the electrode (5), the electrical field intensity near the electrode (5) is changed and performances of the semiconductor device, such as breakdown voltage and reliability, are improved.

摘要翻译： 公开了一种半导体器件及其制造方法。 半导体器件包括：半导体器件有源区（1）; 设置在半导体器件有源区域（1）上的电极形状控制层（2），含有铝的电极形状控制层（2），从半导体器件活性区域向下向上减少铝的含量（ 1），设置在电极形状控制层（2）上的电极区域，朝向半导体器件有源区域（1）延伸并纵向穿过电极形状控制层（2）的槽布置在电极区域中的所有 或凹槽的侧表面的一部分具有直线斜面，从凹槽的中心线突出的凹形斜面和朝向凹槽的中心线突出的凸起斜面之一的形状; 以及电极（5），其全部或部分设置在所述电极区域的所述沟槽中，所述电极（5）具有与所述槽的形状匹配的形状，所述电极（5）的底部与所述半导体器件活动 区域（1）。 通过控制电极（5）的形状，改变电极（5）附近的电场强度，提高了击穿电压和可靠性等半导体器件的性能。

公开(公告)号：EP2157614B1

公开(公告)日：2017-03-01

申请号：EP08776934.5

申请日：2008-05-28

申请人： Nissan Chemical Industries, Ltd.

发明人： MAEDA, Shinichi ,  KISHIOKA, Takahiro

IPC分类号： H01L21/312 ,  C08G59/18 ,  C08L79/04 ,  H01L29/49 ,  C08G73/06 ,  H01L29/51 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

CPC分类号： H01L21/02118 ,  C08G59/182 ,  C08G73/0638 ,  C08G73/0644 ,  C08G73/065 ,  C08G73/0655 ,  C08L79/04 ,  H01L21/312 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7869 ,  H01L51/0021 ,  H01L51/0036 ,  H01L51/0097 ,  H01L51/052 ,  H01L51/0529 ,  H01L51/102

摘要： There is provided a novel gate insulating film forming meterial in consideration of not only initial electric properties immediately after the production of a gate insulating film, but also electric properties after other steps are performed while producing a thin-film transistor using the gate insulating film, and even reliability in the electric properties of the produced element. A gate insulating film forming agent for a thin-film transistor comprising an oligomer compound or a polymer compound, both of which contain a repeating unit having a triazinetrione ring containing a hydroxyalkyl-containing group as a substituent on a nitrogen atom, and a solvent; a gate insulating film produced from the gate insulating film forming agent; a thin-film transistor having the gate insulating film; and a method for producing the gate insulating film or thin-film transistor.

公开(公告)号：EP3109895A3

公开(公告)日：2017-02-15

申请号：EP16177334.6

申请日：2010-11-29

申请人： Intel Corporation

发明人： MURTHY, Anand S. ,  AUBERTINE, Daniel Bourne ,  GHANI, Tahir ,  PETHE, Abhijit Jayant

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/165

CPC分类号： H01L29/7834 ,  H01L21/02057 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/28079 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.