公开(公告)号：EP2219221A4

公开(公告)日：2013-03-13

申请号：EP08855256

申请日：2008-11-06

申请人： PANASONIC CORP

IPC分类号： H01L45/00 ,  H01L27/10

CPC分类号： H01L27/2409 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

公开(公告)号：EP2548226A1

公开(公告)日：2013-01-23

申请号：EP11755583.9

申请日：2011-03-08

申请人： MOSAID Technologies Incorporated

发明人： GILLINGHAM, Peter

IPC分类号： H01L23/50 ,  H01L21/58 ,  H01L27/10

CPC分类号： H01L21/82 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

摘要翻译： 半导体器件具有安装在衬底上的多个堆叠的半导体管芯。 每个芯片都有相似的尺寸。 每个管芯具有沿着管芯的接合边缘布置的第一多个接合焊盘。 将第一组裸片安装到衬底上，其中接合边缘沿第一方向取向。 将第二组裸片安装到衬底上，其中接合边缘沿与第一方向相反的第二方向取向。 每个管芯在第二方向上相对于剩余管芯横向偏移相应的横向偏移距离，使得每个管芯的焊盘不在与基板垂直的方向上设置在基板和剩余管芯的任何部分之间。 多个键合线将键合焊盘连接到衬底。 还公开了一种制造半导体器件的方法。

公开(公告)号：EP2348555B1

公开(公告)日：2013-01-23

申请号：EP11160411.2

申请日：2005-07-21

申请人： Nippon Telegraph And Telephone Corporation

发明人： JIN, Yoshito ,  SAKAI, Hideaki ,  SHIMADA, Masaru

IPC分类号： H01L45/00 ,  C23C14/08 ,  C23C14/35 ,  H01L27/10 ,  H01L27/24 ,  G11C13/00

CPC分类号： C23C14/08 ,  C23C14/357 ,  G11C13/0007 ,  H01L27/101 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/147 ,  H01L45/1625

公开(公告)号：EP2178122B1

公开(公告)日：2012-11-28

申请号：EP08791976.7

申请日：2008-07-31

申请人： Sony Corporation

发明人： OHBA, Kazuhiro ,  MIZUGUCHI, Tetsuya ,  YASUDA, Shuichiro

IPC分类号： H01L27/10 ,  H01L45/00 ,  G11C13/02

CPC分类号： H01L27/101 ,  G11C11/5614 ,  G11C13/0011 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146

公开(公告)号：EP2084745A4

公开(公告)日：2012-10-24

申请号：EP07832713

申请日：2007-11-21

申请人： SEMICONDUCTOR ENERGY LAB

发明人： YUKAWA MIKIO ,  SUGISAWA NOZOMU ,  NAGATA TAKAAKI ,  YOSHITOMI SHUHEI ,  AIZAWA MICHIKO

IPC分类号： H01L27/28 ,  G11C13/00 ,  H01L21/02 ,  H01L21/336 ,  H01L27/10 ,  H01L27/12 ,  H01L29/786 ,  H01L51/05

CPC分类号： H01L51/105 ,  G11C13/0016 ,  G11C13/004 ,  H01L27/283 ,  H01L51/006 ,  H01L51/0591

公开(公告)号：EP2502272A1

公开(公告)日：2012-09-26

申请号：EP10831470.9

申请日：2010-10-29

申请人： Semiconductor Energy Laboratory Co. Ltd.

发明人： KATO, Kiyoshi ,  KOYOMA, Jun

IPC分类号： H01L27/105 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L29/786 ,  H03K3/037 ,  H03K3/356 ,  H03K19/00 ,  H03K19/0948 ,  H03K19/096

CPC分类号： H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

摘要： To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.

摘要翻译： 为了提供一种新颖的非易失性闩锁电路和使用该非易失性闩锁电路的半导体器件，非易失性闩锁电路包括具有其中第一元件的输出端电连接到第二元件的输入端的环路结构的闩锁部分， 所述第二元件的输入端电连接到所述第一元件的输入端; 以及用于保持锁存部分的数据的数据保持部分。 在数据保持部分中，使用氧化物半导体作为用于形成沟道形成区域的半导体材料的晶体管被​​用作开关元件。 另外，包括电连接到晶体管的源电极或漏电极的反相器。 利用晶体管，锁存部分中保存的数据可写入逆变器的栅极电容器或单独提供的电容器。

公开(公告)号：EP2494597A1

公开(公告)日：2012-09-05

申请号：EP10826501.8

申请日：2010-10-05

申请人： Semiconductor Energy Laboratory Co, Ltd.

发明人： YAMAZAKI, Shunpei ,  KOYAMA, Jun ,  KATO, Kiyoshi

IPC分类号： H01L21/8242 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/108 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

摘要翻译： 目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管中的一个的栅极电接触。 包含氧化物半导体层的第一晶体管的非常低的截止电流允许长时间地在第二晶体管和第三晶体管之一的栅极中存储电荷，由此可以获得基本上永久的记忆效应。 不包含氧化物半导体层的第二和第三晶体管在使用存储器电路时允许高速操作。

公开(公告)号：EP2099072A4

公开(公告)日：2012-08-08

申请号：EP07743885

申请日：2007-05-22

申请人： FUJITSU LTD

发明人： NOSHIRO HIDEYUKI

IPC分类号： H01L27/10

CPC分类号： H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1633

公开(公告)号：EP1770778B1

公开(公告)日：2012-03-14

申请号：EP05766330.4

申请日：2005-07-21

申请人： NIPPON TELEGRAPH AND TELEPHONE CORPORATION

发明人： JIN, Yoshito ,  SAKAI, Hideaki, ,  SHIMADA, Masaru

IPC分类号： H01L27/10 ,  H01L21/316 ,  H01L45/00

CPC分类号： C23C14/08 ,  C23C14/357 ,  G11C13/0007 ,  H01L27/101 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/147 ,  H01L45/1625

摘要： A ferroelectric layer (104) is sandwiched by a lower electrode layer (103) and an upper electrode (105), and a prescribed voltage (DC, pulse) is applied between the lower electrode layer (103) and the upper electrode (105) to change the resistance value of the ferroelectric layer (104). When a stable high resistance mode is switched to a low resistance mode, memory operation is performed. Reading can be easily performed by reading a current value at a time when a prescribed voltage is applied on the upper electrode (105).

公开(公告)号：EP1886261B1

公开(公告)日：2011-11-16

申请号：EP06756862.6

申请日：2006-05-25

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： IWATA, Shusuke

IPC分类号： G06K19/07 ,  G06F12/14 ,  G06K19/073 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/10

CPC分类号： G06K19/0723 ,  H01L27/10

摘要： When an operation-stop instruction is received from an RFID reader/writer, an RFID chip decodes the instruction by a control circuit and conducts the operation-stop instruction. In addition, the RFID chip uses a register which has a write-once function such as an organic memory and does not return to an original state physically if a value is written once as a register which maintains a setting whether there is an operation-stop or not.