公开(公告)号：EP1403874A1

公开(公告)日：2004-03-31

申请号：EP03255479.2

申请日：2003-09-02

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Tran, Lung T. ,  Bhattacharyya, Manoj K.

IPC: G11C11/16

CPC classification number: G11C29/028 ,  G11C11/15 ,  G11C11/16 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2029/5006

Abstract: A memory device (50) having a cross point array (100) of memory cells (130) includes a temperature sensor (150) and a reference memory cell (160), the temperature sensor (150) sensing the temperature (T) of the memory device (50) and data from the temperature sensor (150) and the reference memory cell (160) being used to update write currents (IxPA, IyPA, IxAP, IyAP, Ix, Iy) used to program the array (100) of memory cells (130). A method of calibrating the memory device (50) involves detecting a temperature (T) of the memory device (50), determining whether the temperature of the memory device has changed by a threshold value (ΔT), and updating write current values (IxPA, IyPA, IxAP, IyAP, Ix, Iy) if the temperature (T) of the memory device changes by the threshold value (ΔT). The write current values can be updated by data from the reference memory cell (160), or from write current values stored in a lookup table.

Abstract translation: 具有存储器单元（130）的交叉点阵列（100）的存储器装置（50）包括温度传感器（150）和参考存储器单元（160），温度传感器（150）感测温度 存储器装置（50）以及来自温度传感器（150）和参考存储器单元（160）的数据被用于更新用于编程以下各项的阵列（100）的写入电流（IxPA，IyPA，IxAP，IyAP，Ix，Iy）： 存储器单元（130）。 校准存储器装置（50）的方法涉及检测存储器装置（50）的温度（T），确定存储器装置的温度是否已经改变了阈值（ΔT），并且更新写入电流值（IxPA ，IyPA，IxAP，IyAP，Ix，Iy），如果存储器件的温度（T）改变阈值（ΔT）。 写电流值可以通过来自参考存储单元（160）的数据或存储在查找表中的写电流值来更新。

公开(公告)号：EP0929901B1

公开(公告)日：2001-11-28

申请号：EP97945392.5

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, L.

IPC: G11C29/00 ,  G06F11/24 ,  G11C8/00

CPC classification number: G11C29/026 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.

公开(公告)号：EP0997913A1

公开(公告)日：2000-05-03

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Hollandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of:

reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not;
determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell;
the at least one reference memory cell being chosen with a gradually higher threshold;
when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

Abstract translation: 一种用于测试多层存储器件中的原始存储器单元的方法，其包括多个存储器单元，其特殊性包括以下事实：其包括以下步骤：读取构成存储器件的各个存储单元，并将 这些存储单元同时具有至少一个参考存储器单元，以便确定存储器单元的阈值是否低于至少一个参考存储器单元的阈值; 确定阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当发现阈值高于给定参考阈值的存储单元的数量足够低于设置在存储装置中的冗余存储单元的数目时，假设给定参考阈值为存储器件的较低参考阈值，则确定 存储单元阈值的统计分布。

公开(公告)号：EP0616335B1

公开(公告)日：2000-03-29

申请号：EP94101897.0

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke, c/o Fujitsu Limited ,  Yamazaki, Hirokazu, c/o Fujitsu Limited ,  Watanabe, Hisayoshi, c/o Fujitsu Limited ,  Kasa, Yasushi, c/o Fujitsu Limited

IPC: G11C29/00 ,  G11C16/06

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: An object of the present invention is to provide a semiconductor device that permits easy and efficient testing. A nonvolatile semiconductor memory comprises word lines WLi and bit lines BLi, a memory cell matrix 17 consisting of nonvolatile memory cells Cij, a sense amplifier 15, a write/erase timing circuit 9 for performing timing control necessary for write and erase operations, and a status register 2 for storing the operating state of the memory at the completion of the operation of the circuit 9, wherein there are provided, outside the address of the memory cell matrix 17, two kinds of dummy cells, D1, D2, D3,..., whose values are fixed to different values that induce different outputs from the sense amplifier 15. A pass condition or a fail condition is generated by accessing the dummy cells.

公开(公告)号：EP0856188B1

公开(公告)日：1999-10-27

申请号：EP96929800.9

申请日：1996-08-30

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： TANG, Yuan

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3477 ,  G11C16/04 ,  G11C16/28 ,  G11C16/3468 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

公开(公告)号：EP0632464B1

公开(公告)日：1999-09-08

申请号：EP93830278.3

申请日：1993-06-28

Applicant: STMicroelectronics S.r.l.

Inventor： Pezzini, Saverio

IPC: G11C16/06

CPC classification number: G11C29/48 ,  G11C16/04 ,  G11C29/04 ,  G11C29/50 ,  G11C2029/5006

公开(公告)号：EP0929900A1

公开(公告)日：1999-07-21

申请号：EP97945360.0

申请日：1997-09-29

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WENDELL, Dennis, L.

IPC: G06F12 ,  G11C7 ,  G11C8 ,  G11C11 ,  G11C29 ,  H03K3 ,  H03K5 ,  H03L7

CPC classification number: G11C29/026 ,  G06F12/1054 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  G11C11/4087 ,  G11C11/41 ,  G11C11/412 ,  G11C11/418 ,  G11C16/04 ,  G11C17/14 ,  G11C29/02 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/18 ,  G11C29/32 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2029/5004 ,  G11C2029/5006 ,  H03K3/356156 ,  H03K5/13 ,  H03K2005/00019 ,  H03K2005/00071 ,  H03L7/08 ,  H03L7/0995

Abstract: A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds, which is entirely inconsistent with the required economies of manufacturing test. A data retention circuit and method allows high speed test of a static memory cell to ensure that the load devices within the cell are actually present and functioning. An analog word line drive capability allows the active word line to be driven to a user-controllable analog level. This is accomplished by connecting the "VDD" and N-well of the final PMOS stage of the row decoder to an isolated terminal which is normally connected to VDD when assembled , but which is independently available prior to packaging. By lowering the analog word line voltage compared to the memory array power supply voltage, a written high level in a memory cell lacking a load device is not pulled high (because the load device in question is missing) and is already low enough to cause a subsequent read to immediately fail. Consequently, the memory array can be tested without requiring long delays between the write and read of each memory cell. Advantageously, the row and column support circuits and sensing circuits operate at the normal power supply levels for which they were designed and which may be independently margin tested.

公开(公告)号：EP0923082A2

公开(公告)日：1999-06-16

申请号：EP99105425.5

申请日：1994-02-08

Applicant: FUJITSU LIMITED

Inventor： Kumakura, Sinsuke, Fujitsu Limited ,  Yamazaki, Hirokazu, Fujitsu Limited ,  Watanabe, Hisayoshi, Fujitsu Limited ,  Kasa, Yasushi, Fujitsu Limited

IPC: G11C29/00

CPC classification number: G11C29/021 ,  G11C5/14 ,  G11C5/143 ,  G11C7/062 ,  G11C16/04 ,  G11C29/02 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5006

Abstract: A semiconductor memory having a sense amplifier, characterised in that the sense amplifier (41) contains a load resistance section (42) comprising a plurality of load transistors (TP8, TP9) having different load characteristics which are selectable for connection.

Abstract translation: 一种具有读出放大器的半导体存储器，其特征在于，读出放大器（41）包含负载电阻部分（42），负载电阻部分包括具有不同负载特性的多个负载晶体管（TP8，TP9），这些负载特性可选择用于连接。

公开(公告)号：EP0655164B1

公开(公告)日：1998-11-11

申请号：EP94913504.0

申请日：1994-05-06

Applicant: ROBERT BOSCH GMBH

Inventor： BOEHL, Eberhard ,  KESEL, Frank

IPC: G11C29/00 ,  G11C8/00

CPC classification number: G11C29/024 ,  G11C8/10 ,  G11C17/14 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C2029/5006

Abstract: PCT No. PCT/DE94/00521 Sec. 371 Date Jan. 20, 1995 Sec. 102(e) Date Jan. 20, 1995 PCT Filed May 6, 1994 PCT Pub. No. WO94/28555 PCT Pub. Date Dec. 8, 1994A self-test device for memory arrangements, decoders or the like for use during on-line operation, the word lines and/or the column lines of a memory matrix being connected to a check matrix. An error detector which generates an error signal if more than one line is activated simultaneously is connected to the check matrix. Since multiple word lines or column lines are activated in the decoder for most errors which occur, a simple self-test can be performed during on-line operation by this check matrix which can be implemented in a relatively simple and cost-effective manner.

公开(公告)号：EP0543408A3

公开(公告)日：1995-08-09

申请号：EP92119825.5

申请日：1992-11-20

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kushiyama, Natsuki, c/o Intellectual Property Div. ,  Furuyama, Tohru, c/o Intellectual Property Div. ,  Numata, Kenji, c/o Intellectual Property Div.

IPC: G11C29/00

CPC classification number: G11C29/025 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: A semiconductor memory comprises a dynamic type memory cell array (10) arranged to form a matrix and provided with word lines (WL1 to WLm) commonly connected to memory cells (MC) of respective columns and bit lines (BLl through BLn) commonly connected to memory cells of respective rows, a dummy cell section (11) having a first set of dummy word lines (DWL) connected to respective complimentary bit line pairs (BL, /BL) of said memory cell array by way of respective first capacitances (C) and a second set of dummy word lines (/DWL) connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances (C), a dummy word line potential control circuit (15) capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers (SAl to SAn) connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.

Abstract translation: 一种半导体存储器包括：一个动态型存储单元阵列（10），用于形成一个矩阵并提供共同连接到各列的存储单元（MC）和位线（BL1到BLn）的字线（WL1到WLm） 存储器单元，具有通过相应的第一电容（C）连接到所述存储器单元阵列的相应互补位线对（BL，/ BL）的第一组虚拟字线（DWL）的虚拟单元部分（11） ）和通过各自的第二电容（C）连接到所述存储单元阵列的各个互补位线对的第二组虚拟字线（/ DWL），虚拟字线电位控制电路（15），能够可选地控制 当所述存储器单元阵列的所述字线被激活时驱动所选择的虚拟字线的模式，以及连接到所述存储器单元阵列的各个互补位线对用于从选定的m读取数据的读出放大器（SA1到SAn） 存储器单元阵列的存储单元到相关位线上。