摘要:
A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.
摘要:
A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.
摘要:
A semiconductor component comprising a lateral semiconductor device, a vertical semiconductor device, and a leadframe is provided. The lateral semiconductor device has a first side and a second side, and a first electrode, a second electrode, and a control electrode positioned on the first side. The vertical semiconductor device has a first side and a second side, a second electrode and a control electrode of it positioned on the second side and a first electrode of it positioned on the first side. The leadframe electrically and respectively connected to each of the first electrode of the lateral semiconductor device, the second electrode of the lateral semiconductor device, the second electrode of the vertical semiconductor device, and the control electrodes, wherein the first side of the vertical semiconductor device is mounted on the second side of the lateral semiconductor device, and the first electrodes of both devices are electrically connected.
摘要:
A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.
摘要:
A semiconductor device includes a lead frame, a first semiconductor component, a second semiconductor component, and a first conductive member. The lead frame includes a first segment having a first bottom plate, and a second segment having a second bottom plate. The first segment and the second segment are arranged side by side, the first bottom plate is spatially isolated from the second bottom plate, and the first bottom plate is thicker than the second bottom plate. The first semiconductor component is disposed on the first bottom plate, and the second semiconductor component is disposed on the second bottom plate. The second semiconductor component is thicker than the first semiconductor component. The first conductive member electrically connects the second semiconductor component to the first segment.
摘要:
The disclosure provides an embedded package structure comprising a metal substrate (210a), a chip module (220a), an insulation material layer (230a), and at least one patterned metal layer (240a). The metal substrate (210a) has a first surface (211a) and a second surface (212a). The chip module (220a) is disposed on the first surface of the metal substrate, and comprises at least two stacked chips (222a,221a) being electrically connected to each. The insulation material layer (230a) covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection (231a) formed therein. The patterned metal layer (240a) is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure is also disclosed.
摘要:
A package structure including: a first semiconductor device including a first semiconductor substrate and a first electronic device, the first semiconductor device having a first side and a second side, wherein at least part of the first electronic device being adjacent to the first side, and the first semiconductor device has a via-hole formed through the first semiconductor device, wherein the via-hole has a first opening adjacent to the first side; an interconnection structure disposed in the first semiconductor device, wherein the interconnection structure includes: a via structure disposed in the via-hole without exceeding the first opening; a first pad disposed on the first side of the first semiconductor device and covering the via-hole; and a second semiconductor device vertically integrated with the first semiconductor device.
摘要:
The disclosure provides an embedded package structure comprising a metal substrate (210a), a chip module (220a), an insulation material layer (230a), and at least one patterned metal layer (240a). The metal substrate (210a) has a first surface (211a) and a second surface (212a). The chip module (220a) is disposed on the first surface of the metal substrate, and comprises at least two stacked chips (222a,221a) being electrically connected to each. A adhesive layer or a solder (260a) is positioned between the stacked chips. The insulation material layer (230a) covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection (231a) formed therein. The patterned metal layer (240a) is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides.