摘要:
Components having different heights are installed in a multilayer substrate using a metal core layer formed by bonding a plurality of metal layers. The metal core layer includes through-holes and a spot-faced portion. Passive components and an active component are disposed in the through-holes and the spot-faced portion, respectively. These components are connected to conductive patterns formed on wiring layers, with connecting vias therebetween. Contact faces of each component with the connecting vias are controlled so as to be disposed at the same level with the metal layers.
摘要:
Die Erfindung betrifft ein Verfahren zur Herstellung eines Chipmoduls (72,89,) mit einem Trägersubstrat (30, 81) und zumindest einem auf dem Trägersubstrat angeordneten Chip (33) sowie einer Kontaktleiteranordnung (45) zur Verbindung von Chipanschlussflächen (34) mit auf einer Kontaktseite (56) des Chipmoduls angeordneten Anschlusskontakten (69, 70, 71), bei dem die Ausbildung der Kontaktleiteranordnung durch eine Strukturierung einer Kontaktmateriallage (31, 80) des Trägersubstrats erfolgt, wobei vor Ausbildung der Kontaktleiteranordnung (45) zur Ausbildung einer den Chip (33) einhäusenden Hüllmateriallage (35) ein Hüllmaterial auf das Trägersubstrat (30, 81) aufgebracht wird, wobei die Hüllmateriallage (35) von ihrer Oberseite (37) her zur Freilegung einer Chiprückseite (36) Material abtragend bearbeitet wird, derart, dass die Chiprückseite und eine Kontaktsäule (42) bündig in einer durch die Bearbeitung ausgebildeten Hüllmaterialoberfläche (41) angeordnet sind, dass auf die Chiprückseite eine Basismetallisierung (44) aufgebracht wird und dass die Basismetallisierung (44) sowohl auf die Chiprückseite (36) als auch auf die Hüllmaterialoberfläche (41) und die Kontaksäule (42) aufgebracht wird und dass auf die Basismetallisierung eine Kontaktmaterialschicht (43) zur Ausbildung einer Chiprückseitenkontaktleiteranordnung (51, 62) strukturiert wird.
摘要:
A circuit design is logically partitioned into a plurality of blocks. As a first hierarchial assembly level, the blocks are fabricated as individual submodules (20, 21) each including at least one electronic component (22, 24) with component connection pads (26, 28, 30, 32) on a top surface (34, 36), and a first interconnect structure (50) including at least one interconnect layer (56, 58) bonded to the top surfaces (34, 36), and interconnecting selected ones of the component connection pads (26, 28, 30, 32). Submodule connection pads (76) are provided on upper surfaces (78) of the submodules (20, 21). As a second hierarchial assembly level, a second interconnect structure (186) is bonded to the upper surfaces (78) and interconnects selected ones of the submodule connection pads (76).
摘要:
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
摘要:
A resin layer in which adhesion to a conductive film is higher than that of a sealing resin to the conductive film is disposed on the sealing resin in which it is difficult to form the conductive film, and wiring patterns electrically connected to electronic components are disposed on the resin layer.
摘要:
A device embedded substrate (20), includes: an insulation layer (12) including an insulation resin material; an electric or electronic device (4) embedded in the insulation layer (12); a terminal (15) serving as an electrode included in the device (4); a conductor pattern (18) formed on the surface of the insulation layer (12); and a conducting via (21) for electrically connecting the conductor pattern (18) and the terminals (15) with each other. The conducting via (21) is made up of a large-diameter section (21a) having a large diameter and a small-diameter section (21b) having a smaller diameter than that of the large-diameter section (21a), in order starting from the conductor pattern (18) toward the terminal (15). A stepped section (17) is formed between the large-diameter section (21a) and the small-diameter section (21b). The large-diameter section (21a) is formed so as to penetrate a sheet-shaped glass cloth (11) disposed in the insulation layer (12).
摘要:
An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer (102) and a conformal masking layer (112) disposed on at least a portion of the dielectric layer (102). The electronic package further includes a routing layer (136) disposed on at least a portion of the combined masking layer (112) and a micro-via (122) disposed at least in part in the conformal masking layer (112) and the routing layer (136). Further, at least a portion of the routing layer (136) forms a conformal electrically conductive layer (130) in at least a portion of the micro-via (122). Also, the conformal masking layer (112) is configured to define a size of the micro-via (122). The electronic package further includes a semiconductor die (118) operatively coupled to the micro-via (122).
摘要:
Systems and methods are provided for the embedding of thin chips. A well region is generated in a substrate that includes a conductive material disposed on a flexible polymer. The standoff well region can be generated by pattern the conductive material, where the thin chip is embedded in the standoff well region. A cavity can be generated in the polymer layer to form a polymer well region, where the thin chip is embedded in the polymer well region.