公开(公告)号：EP3036766A1

公开(公告)日：2016-06-29

申请号：EP13892033.5

申请日：2013-08-21

申请人： Intel Corporation

发明人： TEH, Weng Hong ,  GUZEK, John S. ,  SANKMAN, Robert L.

IPC分类号： H01L23/48 ,  H01L23/12

CPC分类号： H01L23/5389 ,  H01L21/563 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/8203 ,  H01L2224/82031 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/18162

摘要： Embodiments of the present disclosure are directed towards bumpless interfaces to an embedded silicon die, in integrated circuit (IC) package assemblies. In one embodiment, a method includes forming a surrounding portion of dielectric material defining a cavity therein; placing at least one die in the cavity, the die including a contact; depositing a dielectric material on the die and the surrounding portion; etching the dielectric material to expose the contact; and depositing conductive material onto the contact. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例针对集成电路（IC）封装组件中的嵌入式硅管芯的无扰接口。 在一个实施例中，一种方法包括形成在其中限定空腔的介电材料的周围部分; 将至少一个模具放置在所述空腔中，所述模具包括接触件; 在模具和周围部分上沉积电介质材料; 蚀刻介电材料以暴露接触; 并将导电材料沉积到触点上。 可以描述和/或要求保护其他实施例。

公开(公告)号：EP2769412A1

公开(公告)日：2014-08-27

申请号：EP12788344.5

申请日：2012-10-17

申请人： Invensas Corporation

发明人： CASKEY, Terrence ,  MOHAMMED, Ilyas

IPC分类号： H01L25/10 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/852 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

摘要： A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts.

摘要翻译： 一种微电子封装可包括第一微电子单元包括具有第一芯片触点的半导体芯片，封装剂在所述半导体芯片的边缘接触，以及第一单元在接触所述密封剂的表面露出，并与第一芯片触点电连接。 该包装可包括第二微电子单元包括具有在其表面处的第二芯片触点的半导体芯片，和密封剂的接触在所述第二单元的所述芯片的边缘，并具有一个表面延伸远离边缘。 所述芯片和所述第二单元的密封剂的表面限定的面中的第二单元。 在面部封装端子可以是具有通过与第一单元触点电连接的键合引线的第一部接触，并通过与第二芯片触点接触而形成金属化通孔和迹线的第二芯片触点电连接。

公开(公告)号：EP2865005A4

公开(公告)日：2016-03-30

申请号：EP13809106

申请日：2013-06-25

申请人： RES TRIANGLE INST INT

发明人： VICK ERIC PAUL

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L23/49827 ,  H01L21/02107 ,  H01L21/76898 ,  H01L24/24 ,  H01L24/29 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/80203 ,  H01L2224/8036 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/83203 ,  H01L2224/8336 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H05K3/4661 ,  H01L2224/83

公开(公告)号：EP2854168A2

公开(公告)日：2015-04-01

申请号：EP14184831.7

申请日：2014-09-15

申请人： General Electric Company

发明人： Chauhan, Shakti Singh ,  McConnelee, Paul Alan ,  Gowda, Arun Virupaksha

IPC分类号： H01L23/00 ,  H01L23/538 ,  H05K1/18

CPC分类号： H01L23/5389 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/42 ,  H01L23/433 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/24 ,  H01L24/25 ,  H01L24/26 ,  H01L24/32 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/2518 ,  H01L2224/2732 ,  H01L2224/27416 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8201 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/82101 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/92144 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0266 ,  H05K1/185 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2203/0278 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00

摘要： A package structure (10) includes a dielectric layer (14), at least one semiconductor device (12) attached to the dielectric layer (14), one or more dielectric sheets (26) applied to the dielectric layer (14) and about the semiconductor device(s) (12) to embed the semiconductor device(s) (12) therein, and a plurality of vias (30,36) formed to the semiconductor device(s) (12) that are formed in at least one of the dielectric layer (14) and the one or more dielectric sheets (26). The package structure (10) also includes metal interconnects (38) formed in the vias (30,36) and on one or more outward facing surfaces (18,20) of the package structure (10) to form electrical interconnections to the semiconductor device(s) (12). The dielectric layer (14) is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets (26) is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s) (12).

摘要翻译： 封装结构（10）包括电介质层（14），附着到电介质层（14）的至少一个半导体器件（12），施加到电介质层（14）上的一个或多个电介质片（26） 将半导体器件（12）嵌入其中的半导体器件（12）和形成在半导体器件（12）上的多个通孔（30,36），其形成在至少一个 电介质层（14）和一个或多个电介质片（26）。 封装结构（10）还包括形成在通孔（30,36）中的金属互连（38）和封装结构（10）的一个或多个向外表面（18,20）上，以形成与半导体器件 （12）。 电介质层（14）由在层压工艺期间不流动的材料构成，并且所述一个或多个电介质片（26）中的每一个由可在层压过程中固化时被熔化和流动的可固化材料构成，以便 以填充半导体器件（12）周围的任何气隙。

公开(公告)号：EP2903021A1

公开(公告)日：2015-08-05

申请号：EP14153041.0

申请日：2014-01-29

申请人： J-Devices Corporation

发明人： Inoue, Hiroshi ,  Katsumata, Akio ,  Sawachi, Shigenori ,  Yamagata, Osamu

IPC分类号： H01L23/00 ,  H01L25/10

CPC分类号： H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

摘要： A semiconductor device (100), having an insulating substrate (102); a semiconductor element (101) which is mounted on one main surface of the insulating substrate via adhesive (103), with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer (104a) which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer (105) which is provided on the first insulating material layer (104a) and a portion of which is exposed to an external surface; a first insulating material layer (104b) which is provided on the first metal thin film wire layer (105); a second insulating material layer (107) which is provided on a main surface of the insulating substrate (102) where the semiconductor element is not mounted; a second metal thin film wire layer (106) which is provided inside the second insulating material layer and a portion of which is exposed to an external surface; a via (108) which passes through the insulating substrate and which electrically connects the first metal thin film wire layer (105) in the first insulating material layer (104a) and the second metal thin film wire layer (106); and an external electrode (109) which is formed on the first metal thin film wire layer (105), the semiconductor device having a structure in which the second metal thin film wire layer, an electrode arranged on the element circuit surface of the semiconductor element, the first metal thin film wire layer, the via and the external electrode formed on the first metal thin film wire layer are electrically connected.

摘要翻译： 一种半导体装置（100），具有对绝缘衬底（102）; 其经由粘合剂（103）安装在所述绝缘基片的一个主表面，与面向上的半导体元件的元件电路表面上的半导体元件（101）的所有; 密封该半导体元件的元件电路表面和外周在其上的绝缘基板的第一绝缘材料层（104A）; 其上设置有第一绝缘材料层（104A）和所有的暴露于外部表面上的一部分上的第1金属薄膜层金属线（105）的所有; 其设置在所述第一金属薄膜层金属线（105）的第一绝缘材料层（104B）; 其设置在其中的半导体元件没有被安装在绝缘基板（102）的主表面上的第二绝缘材料层（107）的所有; 该第二绝缘材料层和所有的暴露于外部表面上的部分的内侧设置的第二金属薄膜层金属线（106）的所有; 通孔（108），通过绝缘基板和通过其电连接在所述第一绝缘材料层中的第一金属薄膜层金属线（105）（104A）和所述第二金属薄膜层金属线（106）; 和所有其在第1金属薄膜布线层（105）上形成了外部电极（109），具有在上电极上的第2金属薄膜布线层的半导体元件的元件电路表面上排列的结构的半导体器件 中，第一金属薄膜层金属线，通孔和形成在所述第1金属薄膜层导线与外部电极电连接。

公开(公告)号：EP2865005A1

公开(公告)日：2015-04-29

申请号：EP13809106.1

申请日：2013-06-25

申请人： Research Triangle Institute, International

发明人： VICK, Eric, Paul

IPC分类号： H01L23/12 ,  H01L23/48

CPC分类号： H01L23/49827 ,  H01L21/02107 ,  H01L21/76898 ,  H01L24/24 ,  H01L24/29 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/2919 ,  H01L2224/80203 ,  H01L2224/8036 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/83203 ,  H01L2224/8336 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92144 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/0665 ,  H01L2924/0675 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H05K3/4661 ,  H01L2224/83

摘要： An electronic package may be fabricated by forming a first layer of insulating material on a first substrate such that the first layer covers a contact pad; forming an opening through the first layer to expose the contact pad; forming an un-patterned second layer on the first layer, the second layer including an adhesive having a viscosity less than that of the first layer, wherein a region of the second layer obstructs the contact pad; removing the region to re-expose the contact pad; aligning a second substrate with the first substrate such that a via of the second substrate is aligned with the opening; bonding the first substrate and the second substrate together at the second layer; and forming an interconnect in contact with the contact pad by depositing a conductive material through the via and the opening.

公开(公告)号：EP2733736A2

公开(公告)日：2014-05-21

申请号：EP13005391.1

申请日：2013-11-15

申请人： Siliconfile Technologies Inc.

发明人： Jeon, In Gyun

IPC分类号： H01L23/00 ,  H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention relates to a method for electrically connecting wafers, which physically bonds two wafers through an oxide-to-oxide bonding method and then electrically connects the two wafers through a butting contact structure. The wafers are physically bonded to each other through a relatively simple method, and then electrically connected to through TSVs or butting contact holes. Therefore, since the fabrication process may be simplified, a process error may be reduced, and the product yield may be improved.

摘要翻译： 本发明涉及到用于电连接晶片的方法，其中物理地通过到氧化物到氧化物接合方法粘合两个晶片，然后电通过对接接触结构的两个晶片相连接。 晶片被物理地通过相对简单的方法彼此结合，然后电连接到通过硅通孔或对接接触孔。 因此，由于制造工艺可以被简化，加工误差可能会降低，产品的成品率可以得到改善。

公开(公告)号：EP2731128A2

公开(公告)日：2014-05-14

申请号：EP13191628.0

申请日：2013-11-05

申请人： General Electric Company

发明人： Delgado, Eladio Clemente ,  Glaser, John Stanley ,  Rowden, Brian Lynn

IPC分类号： H01L23/00 ,  H01L23/433

CPC分类号： H01L24/19 ,  H01L23/3735 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A surface mount package (10,70,80) includes at least one semiconductor device (12) and a POL packaging and interconnect system (20) formed about the at least one semiconductor device (12) that is configured enable mounting of the surface mount package to an external circuit. The POL system (20) includes a dielectric layer (24,82) overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias (28) formed through the dielectric layer (24,82) so as to be electrically coupled to connection pads (30) on the semiconductor device(s). A metallization layer (34) is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate (54) is positioned on a second surface of the semiconductor device(s) (12), with the double-sided ceramic substrate (54) being configured to electrically isolate a drain (64) of the semiconductor device(s) from an external circuit (50) when the surface mount package (10,70,80) is joined thereto and to conduct heat away from the semiconductor device(s) (12).

摘要翻译： 表面安装封装（10,70,80）包括至少一个半导体器件（12）和围绕所述至少一个半导体器件（12）形成的POL封装和互连系统（20），所述半导体器件被配置为能够安装表面安装 封装到外部电路。 POL系统（20）包括覆盖在半导体器件的第一表面上的电介质层（24,82）和延伸穿过通过介电层（24,82）形成的通孔（28）的金属互连结构，从而 电耦合到半导体器件上的连接焊盘（30）。 金属化层（34）形成在包括平坦平面结构的金属互连结构之上，并且双面陶瓷衬底（54）位于半导体器件（12）的第二表面上，具有双 （54）被配置为当所述表面安装封装（10,70,80）连接到所述半导体器件的漏极（64）并将其导热，从而将所述半导体器件的漏极（64）与外部电路（50）电隔离 远离半导体器件（12）。

公开(公告)号：EP2731128A3

公开(公告)日：2018-02-07

申请号：EP13191628.0

申请日：2013-11-05

申请人： General Electric Company

发明人： Delgado, Eladio Clemente ,  Glaser, John Stanley ,  Rowden, Brian Lynn

IPC分类号： H01L23/00 ,  H01L23/433

CPC分类号： H01L24/19 ,  H01L23/3735 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

摘要： A surface mount package (10,70,80) includes at least one semiconductor device (12) and a POL packaging and interconnect system (20) formed about the at least one semiconductor device (12) that is configured enable mounting of the surface mount package to an external circuit. The POL system (20) includes a dielectric layer (24,82) overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias (28) formed through the dielectric layer (24,82) so as to be electrically coupled to connection pads (30) on the semiconductor device(s). A metallization layer (34) is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate (54) is positioned on a second surface of the semiconductor device(s) (12), with the double-sided ceramic substrate (54) being configured to electrically isolate a drain (64) of the semiconductor device(s) from an external circuit (50) when the surface mount package (10,70,80) is joined thereto and to conduct heat away from the semiconductor device(s) (12).

摘要翻译： 表面安装封装（10,70,80）包括围绕所述至少一个半导体器件（12）形成的至少一个半导体器件（12）和POL封装和互连系统（20），所述至少一个半导体器件被构造成能够安装表面安装 封装到外部电路。 POL系统（20）包括覆盖半导体器件的第一表面的介电层（24,82）和延伸穿过介电层（24,82）形成的通孔（28）的金属互连结构，以便 被电耦合到半导体器件上的连接焊盘（30）。 在包括平坦平面结构的金属互连结构上形成金属化层（34），并且双面陶瓷衬底（54）位于半导体器件（12）的第二表面上，双层陶瓷衬底 当所述表面安装封装（10,70,80）连接到所述半导体器件时，所述半导体器件的漏极（64）与外部电路（50）电隔离并且传导热量 远离半导体器件（12）。

公开(公告)号：EP2733736A3

公开(公告)日：2018-01-24

申请号：EP13005391.1

申请日：2013-11-15

申请人： SK hynix Inc.

发明人： Jeon, In Gyun

IPC分类号： H01L21/60 ,  H01L23/48 ,  H01L27/146 ,  H01L21/768 ,  H01L21/822

CPC分类号： H01L25/50 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/06 ,  H01L24/07 ,  H01L24/08 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L27/14612 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/06051 ,  H01L2224/06505 ,  H01L2224/06517 ,  H01L2224/08146 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/82031 ,  H01L2224/821 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/053 ,  H01L2224/05552 ,  H01L2924/00

摘要： The present invention relates to a method for electrically connecting wafers, which physically bonds two wafers through an oxide-to-oxide bonding method and then electrically connects the two wafers through a butting contact structure. The wafers are physically bonded to each other through a relatively simple method, and then electrically connected to through TSVs or butting contact holes. Therefore, since the fabrication process may be simplified, a process error may be reduced, and the product yield may be improved.

摘要翻译： 本发明涉及一种用于电连接晶片的方法，晶片通过氧化物到氧化物键合方法物理键合两个晶片，然后通过对接接触结构电连接两个晶片。 晶片通过相对简单的方法彼此物理结合，然后通过TSV或对接接触孔电连接。 因此，由于可以简化制造工艺，所以可以减少工艺误差，并且可以提高产品产量。